Silicided Gettering Regions on SOI Substrates for Metal Contaminant Trapping
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Solution Overview
Problem
CMOS image sensors on silicon on insulator (SOI) substrates face contamination from metal impurities during manufacturing, which can lead to defects such as Dark Currents and 'Bright Pixel' effects due to metal contaminants remaining near active areas, and existing gettering techniques are ineffective for SOI wafers with Back-Side illuminated CMOS image sensors.
Innovation Solution
Creating silicided gettering regions on non-leakage-sensitive areas within pixels and connecting them with active area connectors to form a continuous active area, allowing metal contaminants to migrate and be trapped in gettering regions, which are formed at a distance from leakage-sensitive components to prevent leakage, and heating the wafer to trap contaminants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing gettering techniques are used on SOI wafers, then manufacturing process is simplified, but metal contaminant removal is ineffective
Solution Approach 1:
The invention divides the SOI wafer surface into distinct functional zones: active areas for pixel formation, non-active areas for gettering, and isolation regions. This segmentation allows metal contaminants to be directed to specific gettering regions while preserving active pixel areas, solving the contradiction by making contaminant removal effective without requiring complex trench isolation structures.
Solution Approach 2:
The invention introduces an intermediary layer or region between the active pixel areas and the substrate, which serves as a gettering zone. This intermediary structure captures metal contaminants during manufacturing processes, effectively removing them from active areas while maintaining a relatively simple manufacturing process that builds upon existing SOI fabrication techniques.
2Reliability
If gettering regions are placed close to active areas, then contaminant trapping is enhanced, but leakage currents increase
Solution Approach 1:
The invention applies different properties to different regions of the wafer: active areas are optimized for pixel performance with high purity requirements, while non-active gettering areas are designed to attract and trap metal contaminants. The isolation regions between these zones provide gradual transitions and prevent direct interaction, allowing efficient contaminant trapping while maintaining low leakage currents in active areas through localized property differentiation.
Solution Approach 2:
The invention extracts the gettering function from the active pixel areas and places it in separate non-active regions. By removing the contaminant-trapping function from the sensitive active areas and locating it in dedicated gettering zones, the system achieves efficient contaminant removal without exposing leakage-sensitive components to potential contamination or electrical interference.
3Object-affected harmful factors
If trench isolation is used to separate gettering regions, then leakage is prevented, but manufacturing complexity increases
Solution Approach 1:
Instead of using complex trench isolation structures to separate gettering regions from active areas, the invention inverts the approach by using the natural SOI buried oxide layer and strategically placed metal layers as the primary isolation mechanism. The metal interconnect layers and dielectric layers in the SOI structure itself provide sufficient electrical isolation, eliminating the need for additional trench isolation steps and reducing manufacturing complexity while still preventing leakage currents.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and uniform gettering of metal contaminants, reducing defect pixels and improving the performance of CMOS image sensors by effectively removing contaminants from active areas without damaging the SOI wafer or requiring trench isolation.
Implementation Method 1
allowing metal contaminants to migrate and be trapped in gettering regions
Implementation Method 2
heating the wafer to trap contaminants
Data Source
AI summary
Some demonstrative embodiments include devices and/or methods of gettering on silicon on insulator (SOI) substrate. For example, a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) may include a plurality of pixels arranged on a wafer, a pixel of the pixels including: a silicon active area; at least one non-silicided leakage-sensitive component formed on the active area, the leakage-sensitive component is sensitive to metal contaminants; a non-leakage-sensitive area formed on the active area, the non-leakage-sensitive area surrounding the leakage-sensitive component; and at least one silicided gettering region formed on the non-leakage-sensitive area to trap the metal contaminants.