SOI SRAM Transistor Leakage Control via Segmented Wells
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Solution Overview
Problem
The use of a double-gate structure in semiconductor devices on SOI substrates for CMOS and SRAM applications faces challenges with leakage current due to forward bias of the PN junction, particularly when trying to control the threshold voltage effectively in memory cells with multiple transistors.
Innovation Solution
The semiconductor device employs a configuration where transistors are coupled with back gate regions and well regions to control the threshold voltage dynamically, reducing leakage current and improving switching characteristics by avoiding forward bias between the well regions and back gate regions, and using a lightly doped drain (LDD) structure for source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a double-gate structure is used to control threshold voltage in SOI-based CMOS/SRAM devices, then threshold voltage controllability is improved, but leakage current increases due to forward bias of the PN junction
Solution Approach 1:
The device is divided into separate first and second well regions with opposite conductivity types, each independently controllable. This segmentation allows the PN junction between well regions to be avoided or controlled, preventing forward bias-induced leakage current while maintaining threshold voltage controllability through independent well region potential control.
Solution Approach 2:
An insulating layer is introduced between the first and second well regions to prevent direct electrical contact and form a PN junction. This intermediary structure eliminates the forward bias leakage current path while still allowing each well region to independently control its respective transistor's threshold voltage through separate potential application.
2Manufacturing precision
If well regions are used to control substrate potential for threshold voltage adjustment, then threshold voltage control is improved, but forward bias of PN junction causes leakage current
Solution Approach 1:
The harmful PN junction interface is extracted or eliminated by introducing an insulating layer between well regions of opposite conductivity types. This removes the source of forward bias leakage current while preserving the useful function of independent well region potential control for threshold voltage adjustment.
Solution Approach 2:
An insulating layer serves as an intermediary barrier between first and second well regions, preventing charge carrier injection across the junction that would occur under forward bias. This intermediary structure eliminates energy loss through leakage current while maintaining threshold voltage control capability.
3Reliability
If LDD structure is used in source/drain regions, then hot carrier effects are reduced and device reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The LDD structure applies local quality by creating lightly doped regions specifically in the source/drain areas adjacent to the channel, rather than uniform doping throughout. This localized light doping reduces peak electric fields and hot carrier effects at critical locations while maintaining overall device functionality, with the added benefit that the opposite conductivity type well regions further suppress hot carrier injection.
Data Source
AI summary
A semiconductor device with an SRAM memory cell having improved characteristics.Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.