SOI Substrate Contact Structure for Static Charge Dissipation
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Solution Overview
Problem
Static charges can build up in the support substrate of silicon-on-insulator (SOI) semiconductor devices, disrupting normal chip operation due to the 'floating' configuration of the support substrate, which is not electrically connected and lacks grounding.
Innovation Solution
A substrate contact structure is formed that passes through the top surface layer, insulator layer, and isolation region to contact a doped region in the support substrate, and is connected to a conductive line at a desired potential, such as ground, to prevent charging of the support substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the support substrate is isolated by an insulator layer to reduce parasitic capacitance, then device performance is improved, but the support substrate becomes electrically floating and accumulates static charges that disrupt normal operation
Solution Approach 1:
A substrate contact structure serves as an intermediary element that bridges the isolated support substrate and the external ground potential. This contact structure penetrates through the insulator layer and isolation regions to establish an electrical connection, allowing static charges to be dissipated while maintaining the beneficial electrical isolation provided by the insulator layer for parasitic capacitance reduction.
Solution Approach 2:
The harmful static charge accumulation is extracted from the support substrate by providing a dedicated grounding path through the substrate contact structure. This allows the support substrate to maintain its isolated configuration for low parasitic capacitance while simultaneously removing the harmful effect of charge buildup through the extraction pathway provided by the contact structure connected to ground potential.
2Object-generated harmful factors
If the support substrate is electrically connected to ground to prevent static charge buildup, then reliable operation is ensured, but the electrical isolation provided by the insulator layer is compromised
Solution Approach 1:
The substrate contact structure implements local grounding only in specific regions where isolation regions are present, rather than grounding the entire support substrate uniformly. This localized approach allows the insulator layer to maintain electrical isolation in active device regions while providing grounding pathways only in areas where isolation regions exist, thus preventing static charge buildup without compromising the overall electrical isolation required for device reliability.
3Object-generated harmful factors
If a substrate contact structure is added to ground the support substrate, then static charge buildup is prevented, but device complexity increases
Solution Approach 1:
The substrate contact structure is merged with existing isolation regions and integrated into the conventional SOI device architecture. By combining the grounding function with the existing isolation structure, the patent adds minimal complexity while effectively preventing static charge buildup. The contact structure utilizes the same fabrication processes and material layers already present in the device, avoiding the need for separate complex grounding mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively grounds the SOI substrate, preventing erratic behavior and ensuring normal operation of semiconductor devices by eliminating static charge buildup, particularly in RF devices.
Implementation Method 1
The substrate contact structure is connected to at least one conductive line with a desired potential to prevent charging of the support substrate at system level
Data Source
AI summary
Devices and methods for forming a device are presented. The method includes providing a substrate having at least a first region and a second region prepared with isolation regions. The first region is referred to as a chip guarding area and the second region defines a chip region of which at least one transistor is to be formed. The substrate includes a top surface layer, a support substrate and an insulator layer in between them. A transistor is formed in the second region and a substrate contact structure is formed in the first region. The substrate contact structure passes through at least the top surface layer, insulator layer and isolation region and contacts a doped region in the support substrate. The substrate contact structure is connected to at least one conductive line with a desired potential to prevent charging of the support substrate at system level.