SOI Substrate Contacts via Stress-Inducing Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of substrate contacts in SOI integrated circuits is challenging due to the buried insulating layer, which reduces heat dissipation and can result in substrate contacts that marginally extend to the silicon substrate, impacting performance and robustness, especially in high-performance devices like microprocessors.
Innovation Solution
The method involves forming a first trench in the SOI substrate to the silicon substrate, depositing stress-inducing layers with different intrinsic stresses, and filling a second trench with conductive material, using these layers as spacers to reduce the etch depth through the interlayer dielectric material and improve substrate contact robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deeper etch through interlayer dielectric material is performed to reach silicon substrate, then substrate contact formation is achieved, but etch depth increases making the process more challenging and resulting in marginal contact extension
Solution Approach 1:
The patent introduces an intermediary layer (silicon nitride stress-inducing layer) between the interlayer dielectric material and the silicon substrate. This intermediary layer serves as a spacer that reduces the required etch depth through the interlayer dielectric material while still enabling reliable substrate contact formation. The intermediary layer mediates between the conflicting requirements of deep etching for contact formation and precise etch control for manufacturing reliability.
2Reliability
If buried insulating layer is used in SOI substrate, then device performance is improved with lower junction capacitance, but heat dissipation capability is reduced
Solution Approach 1:
The silicon nitride stress-inducing layer acts as a thermal intermediary that facilitates heat dissipation from the silicon substrate while maintaining the electrical isolation provided by the buried insulating layer. This intermediary structure allows the system to benefit from both the electrical performance improvements of SOI devices and enhanced thermal management capabilities.
Solution Approach 2:
The patent changes the physical and chemical parameters of the substrate structure by introducing stress-inducing layers with specific stress characteristics. These parameter changes in the substrate structure enable improved heat dissipation while maintaining the low junction capacitance benefits of the SOI configuration.
3Ease of manufacture
If substrate contacts are formed contemporaneously with device contacts, then process integration is simplified, but etch depth variability impacts contact quality
Solution Approach 1:
The patent applies preliminary action by forming the silicon nitride stress-inducing layer and metal silicide region before etching the substrate contact trenches. This preliminary structuring establishes precise reference planes and depth markers that guide subsequent etching operations, ensuring consistent contact formation across all contacts (both device and substrate contacts) while maintaining process integration.
Solution Approach 2:
The stress-inducing layer serves as a mediator that decouples the etching processes for device contacts and substrate contacts. By providing a common reference structure, it enables both contact types to be formed in an integrated manner while eliminating the precision problems caused by etch depth variability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of substrate contacts with improved robustness and reduced etch depth through the interlayer dielectric material, enhancing the performance and reliability of high-performance devices by maintaining effective temperature sensing across the substrate.
Implementation Method 1
A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. The second stress-inducing layer has a different type of intrinsic stress than the first stress-inducing layer.
Data Source
AI summary
Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts are provided. One method includes forming a first trench in a SOI substrate extending through a buried insulating layer to a silicon substrate. A metal silicide region is formed in the silicon substrate exposed by the first trench. A first stress-inducing layer is formed overlying the metal silicide region. A second stress-inducing layer is formed overlying the first stress-inducing layer. An ILD layer of dielectric material is formed overlying the second stress-inducing layer. A second trench is formed extending through the ILD layer and the first and second stress-inducing layers to the metal silicide region. The second trench is filled with a conductive material.