SOI Substrate Deuterium Doping Reduces Parasitic Capacitance
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Solution Overview
Problem
Current methods for manufacturing silicon on insulator (SOI) substrates either increase the cost due to high deuterium pressure requirements or fail to effectively reduce parasitic capacitance between the drain region and the substrate.
Innovation Solution
A method involving ion beam doping of a semiconductor substrate with hydrogen to form a doping layer, followed by bonding with another substrate, annealing in a deuterium atmosphere, and separating to create a deuterium doped layer, which reduces parasitic capacitance and lowers manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If annealing is performed in a deuterium atmosphere to remove dangling bonds, then the reliability of the semiconductor device is improved, but the manufacturing cost increases due to very high deuterium pressure requirements
Solution Approach 1:
The patent changes the pressure parameter of the deuterium atmosphere from very high pressure to atmospheric pressure or low pressure conditions. This parameter change maintains the effectiveness of dangling bond removal while dramatically reducing manufacturing costs and equipment requirements
Solution Approach 2:
The patent uses deuterium doping as a substitute approach that replicates the beneficial effects of high-pressure deuterium annealing through a different mechanism - ion implantation followed by low-pressure annealing achieves similar dangling bond removal without requiring extreme pressure conditions
2Manufacturing precision
If hydrogen ions are doped into a silicon wafer to form an ion doped layer, then a monocrystalline silicon film can be formed, but the parasitic capacitance between the drain region and substrate is not effectively reduced
Solution Approach 1:
The patent creates a composite structure with multiple doped layers - a first ion-doped layer for monocrystalline formation and a second deuterium-doped layer for parasitic capacitance reduction. This composite doping approach simultaneously achieves both objectives that single-doping methods cannot accomplish
Solution Approach 2:
The patent applies different doping strategies to different regions and depths: hydrogen ion doping at specific depths for crystal structure control, and deuterium doping at the interface region specifically targeted at reducing parasitic capacitance. Each doping layer has localized functionality optimized for its specific purpose
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance and enhances the resilience of semiconductor devices to hot carrier effects while minimizing production costs by eliminating dangling bonds through deuterium doping without requiring high deuterium pressure.
Implementation Method 1
irradiating the first semiconductor substrate via a ion beam for forming a doping layer
Implementation Method 2
annealing the first wafer and second wafer at a deuterium atmosphere
Implementation Method 3
forming a deuterium doped layer on the second wafer
Data Source
AI summary
This invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; irradiating the first semiconductor substrate via a ion beam for forming a doping layer to a pre-determined depth from a top surface of the first insulating layer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer at a deuterium atmosphere; separating a part of the first wafer from the second wafer; and forming a deuterium doped layer on the second wafer.