SOI Transistor Substrates With Multi-Depth Buried Oxide Layers
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Solution Overview
Problem
Existing semiconductor technologies face challenges in fabricating Silicon on Insulator (SOI) devices with controlled quality overlaying silicon layers, limiting their applications and increasing manufacturing costs due to the need for multiple substrates for different operating modes.
Innovation Solution
The method involves forming multiple buried oxide (BOX) structures in a bulk silicon substrate through doping and epitaxial growth, allowing for the creation of both fully depleted and partially depleted SOI transistors on a single substrate, with BOXes formed at different depths to enhance mechanical stress tolerance and integration capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple substrates are used for different operating modes, then device functionality is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple SOI device types (fully depleted and partially depleted transistors) onto a single substrate by forming multiple buried oxide layers at different depths within the silicon substrate. This merging approach eliminates the need for separate substrates for different operating modes, thereby reducing manufacturing costs while maintaining device functionality.
Solution Approach 2:
The single substrate is designed to support multiple operating modes through the formation of multiple BOX structures at different depths. The universal substrate can accommodate both fully depleted SOI devices (using the first BOX) and partially depleted SOI devices (using the second BOX), providing multi-functionality without requiring separate specialized substrates.
2Ease of manufacture
If single substrate is used for multiple operating modes, then manufacturing cost is reduced, but control of silicon layer quality is limited
Solution Approach 1:
The patent applies local quality by forming multiple buried oxide layers at specific depths within the silicon substrate. Each BOX is positioned at a different depth to create locally optimized regions: the first BOX for fully depleted mode and the second BOX for partially depleted mode. This allows different quality characteristics in different regions of the same substrate.
Solution Approach 2:
The silicon substrate is segmented into multiple functional regions by forming discrete buried oxide layers at different depths. This segmentation allows independent control and optimization of silicon layer quality for each operating mode within the same substrate, addressing the limitation of uniform quality control in single-mode substrates.
3Strength
If multiple BOX structures are formed at different depths, then mechanical stress tolerance is improved, but device complexity increases
Solution Approach 1:
The patent employs a nested structure where multiple buried oxide layers are positioned at different depths within the silicon substrate, similar to nested dolls. The first BOX is formed at a first depth and the second BOX at a second depth, creating a hierarchical nested arrangement that enhances mechanical stress tolerance while organizing complexity in a structured manner.
Solution Approach 2:
The patent resolves structural complexity by transitioning from a two-dimensional surface arrangement to a three-dimensional depth-based arrangement. Multiple BOX structures are positioned at different depths (vertical dimension) rather than spreading out horizontally, which enhances mechanical stress tolerance through vertical distribution while maintaining compact device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of SOI devices with improved mechanical stress tolerance and reduced manufacturing costs by allowing multiple transistor types to be integrated on a single substrate, addressing the limitations of existing technologies in controlling silicon layer quality and reducing the need for multiple substrates.
Implementation Method 1
doping a first region of a first silicon layer with first n-type dopants
Implementation Method 2
epitaxially growing a second silicon layer over the first silicon layer
Implementation Method 3
selectively etching the first region of the first silicon layer
Implementation Method 4
forming a first oxide layer in the first region
Data Source
AI summary
A semiconductor device includes a transistor, which includes a gate structure, a first source/drain structure, and a second source/drain structure. The gate structure is laterally disposed between the first source/drain structure and the second source/drain structure. The first source/drain structure and the second source/drain structure are formed in a first silicon layer disposed over a second silicon layer. The first silicon layer having at least a portion in direct contact with the second silicon layer. The second silicon layer includes a plurality of buried oxide layers.