SOI Switch LNA Module With SiGe LNA for Low-Noise 5G RF Integration

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Solution Overview

Problem

Current semiconductor technologies for 5G-NR, such as group III-V semiconductors, face issues like high power consumption, low integration level, difficulty in mass production, and high costs, while silicon on insulator (SOI) technology offers reduced parasitic capacitance and improved power-speed performance but requires innovative integration for high-frequency RF communication circuits.

Innovation Solution

A switch LNA module utilizing SOI transistors and SiGe transistors in a cascode structure, with a buried oxide layer and thick metal layers for improved heat conduction and noise reduction, integrated with passive components to enhance performance for 5G telecommunications systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If group III-V semiconductor technologies (e.g. GaAs) are used for 5G, then high frequency performance is achieved, but power consumption increases and integration level decreases

Engineering Contradiction:
Improvefrequency performanceVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent changes the material parameter from group III-V semiconductors to silicon-based materials, and changes the structural parameter by introducing SOI technology with buried oxide layers, achieving high frequency performance with reduced power consumption

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses composite structure combining silicon active layer with buried oxide layer (SOI), and integrates SiGe transistors with passive components on the same substrate, achieving both high frequency performance and low power consumption through material composition optimization

Inventive Principle:
Principle #40Composite materials

2Speed

If group III-V semiconductor technologies (e.g. GaAs) are used for 5G, then high frequency performance is achieved, but integration level decreases

Engineering Contradiction:
Improvefrequency performanceVSAvoidintegration level
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent merges active devices (SiGe transistors) and passive components (inductors, capacitors, resistors) into a single integrated circuit on silicon substrate, achieving high integration level while maintaining high frequency performance through unified design and fabrication process

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal silicon-based platform that can simultaneously support high frequency operation, low power consumption, and high integration of multiple circuit functions, replacing the need for separate group III-V devices

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If conventional silicon technology is used, then cost-effectiveness is maintained, but parasitic capacitance increases reducing power-speed performance

Engineering Contradiction:
Improvecost-effectivenessVSAvoidpower-speed performance
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The patent changes the electrical parameter by introducing buried oxide layer that reduces parasitic capacitance between active silicon layer and substrate, thereby improving power-speed performance while maintaining silicon-based cost-effectiveness

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The buried oxide layer acts as an intermediary that electrically isolates the active silicon layer from the substrate, reducing parasitic capacitance and improving high frequency performance while maintaining the benefits of silicon technology

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution provides a low noise figure and improved linearity, meeting 5G system requirements with reduced power consumption and increased integration level, while maintaining cost-effectiveness and efficient heat management.

Implementation Method 1

thick metal layers for improved heat conduction

Methodology Applied
Scientific EffectHeat conduction: Conduction (thermal)

Data Source

PatentUS20240153957A1Switch LNA module
Publication Date: 2024.05.09 X FAB FRANCE SAS
  • US20240153957A1 patent drawing
  • US20240153957A1 patent drawing
  • US20240153957A1 patent drawing

AI summary

A switch LNA module including a silicon on insulator, SOI, wafer having a silicon substrate and an active layer separated by a buried oxide, BOX, layer, wherein the SOI substrate is a high resistance, HR, SOI substrate having a silicon handle wafer with a resistivity greater than 1 kΩ-cm. The switch LNA module further includes a switch having a plurality of SOI transistors, a low noise amplifier, LNA, located in the SOI wafer and connected to an output of the switch. The LNA includes a bipolar transistor formed in a bulk region of the SOI wafer where the BOX layer is removed. The switch LNA module further includes a thick metal layer for connecting to the switch and to the LNA.