SOI Tap Cell Placement to Eliminate Poly Debris
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Solution Overview
Problem
Conventional techniques for forming contacts to semiconductor bulk substrates in SOI devices result in wafer pollution due to the formation of unstable poly ridges in large BOX openings, which complicates the manufacturing process and leads to contamination.
Innovation Solution
The solution involves forming tap cells to provide electrical connections between N-doped and P-doped regions and a biasing voltage network, with the tap cells positioned outside the regular poly line grid, avoiding the formation of poly material in BOX layer openings and thus preventing poly debris from forming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional techniques are used to form contacts to semiconductor bulk substrates in SOI devices, then electrical connections can be established, but wafer pollution occurs due to formation of unstable poly ridges in large BOX openings
Solution Approach 1:
The patent extracts the problematic poly ridge formation by repositioning the tap cell contacts outside the regular poly line grid area. By placing contacts in boundary cells rather than within the active poly grid, the poly material deposition process no longer creates unstable poly ridges over the contact openings, thereby eliminating the source of wafer pollution while maintaining electrical connection functionality.
Solution Approach 2:
The patent introduces boundary cells as intermediary structures between the regular poly line grid and the substrate contact regions. These boundary cells act as a buffer zone that prevents poly material from interacting with the contact openings, serving as a mediator that allows electrical connections to be formed without generating poly debris contamination.
2Adaptability or versatility
If tap cells are positioned within the regular poly line grid, then standard cell layout is maintained, but poly debris is generated during manufacturing
Solution Approach 1:
The patent segments the cell layout into distinct functional zones: regular standard cells within the poly line grid for logic functions, and separate boundary cells for substrate contacts. This segmentation allows the poly line grid to maintain its regular pattern for standardization while the boundary cells provide dedicated contact regions free from poly debris generation.
3Reliability
If large BOX openings are formed for substrate contacts, then electrical access to bulk substrate is achieved, but unstable poly ridges form causing contamination
Solution Approach 1:
The patent removes the conflict between large BOX openings and poly ridge stability by extracting the contacts from the poly line grid area. The large openings are maintained for substrate access, but their location is moved to boundary cells where no poly material is deposited, eliminating poly ridge formation entirely while preserving contact accessibility.
Data Source
AI summary
An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.