Semiconductor-on-insulator thickness uniformity via sacrificial oxide mapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current processes for standardizing the thickness of ultrathin semiconductor layers in fully depleted semiconductor-on-insulator (SeOI) structures lack the necessary precision and uniformity, particularly in industrial-scale manufacturing, with existing methods achieving variability of ±1 nm to 1.5 nm, which is beyond the desired accuracy of ±0.5 nm for FD SeOI applications.
Innovation Solution
A process involving measuring the thickness of the sacrificial oxide and semiconductor layers at multiple points, sorting structures into thickness classes, and performing chemical etching under adjusted conditions to standardize the semiconductor layer thickness, using SC1 etching with hydrofluoric acid and localized heating to achieve precise thinning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sacrificial oxidation is used to correct semiconductor layer thickness, then thickness control is improved, but manufacturing precision deteriorates due to temperature non-uniformity in batch equipment
Solution Approach 1:
The patent implements a feedback mechanism by measuring the thickness of the sacrificial oxide layer formed during oxidation, using this measurement to determine the actual thickness of the semiconductor layer, and then adjusting subsequent etching parameters based on this feedback to achieve the target thickness with high precision
Solution Approach 2:
The patent replaces thermal oxidation in batch ovens with plasma-based oxidation followed by selective etching. This substitution eliminates temperature non-uniformity issues by using a non-thermal process, thereby achieving better thickness uniformity while maintaining the ability to control layer thickness
2Productivity
If batch-type sacrificial oxidation is used for thinning, then productivity is improved, but manufacturing precision deteriorates with variability of ±1 nm to 1.5 nm
Solution Approach 1:
The patent changes the oxidation parameters by using plasma-based oxidation instead of thermal oxidation, and adjusts the etching parameters (time, temperature, chemistry) to achieve precise thickness control. This allows maintaining batch processing productivity while achieving thickness uniformity of ±0.5 nm or better
Solution Approach 2:
The patent performs preliminary formation of the sacrificial oxide layer with controlled thickness, then uses selective etching to remove this layer along with an additional layer of semiconductor material. This preliminary action allows precise control of the final semiconductor layer thickness while maintaining high productivity through batch processing
3Reliability
If ultrathin semiconductor layers are used for FD SeOI structures, then device performance is improved, but thickness uniformity control becomes more difficult
Solution Approach 1:
The patent uses a sacrificial oxide layer as an intermediary medium. This layer is formed on the semiconductor substrate, then selectively removed to achieve precise thinning of the semiconductor layer. The intermediary layer enables controlled removal of material to achieve the required ultrathin dimensions with high uniformity
Solution Approach 2:
The patent replaces mechanical or purely thermal thinning methods with a chemical etching process that selectively removes the sacrificial oxide layer. This substitution enables precise control of ultrathin layer thickness with minimal variability, achieving the required ±0.5 nm or better uniformity for device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process achieves a significant reduction in thickness variability to within ±0.5 nm or less, ensuring uniformity across multiple wafers and batches, meeting the stringent requirements for FD SeOI structures while maintaining compatibility with existing manufacturing processes.
Implementation Method 1
carrying out a chemical etching of the semiconductor layer, the application, temperature and/or duration conditions of which are adjusted as a function of the mapping and/or of the mean thickness of the semiconductor layer
Implementation Method 2
the application, temperature and/or duration conditions of which are adjusted as a function of the mapping and/or of the mean thickness of the semiconductor layer
Data Source
AI summary
The invention relates to a process for treating a structure of semiconductor-on-insulator type successively comprising a support substrate, a dielectric layer and a semiconductor layer having a thickness of less than or equal to 100 nm, the semiconductor layer being covered with a sacrificial oxide layer, comprising measuring, at a plurality of points distributed over the surface of the structure, the thickness of the sacrificial oxide layer and of the semiconductor layer, so as to produce a mapping of the thickness of the semiconductor layer and to determine, from the measurements, the average thickness of the semiconductor layer, selective etching of the sacrificial oxide layer so as to expose the semiconductor layer, and carrying out a chemical etching of the semiconductor layer, the application, temperature and/or duration conditions of which are adjusted as a function of the mapping and/or of the mean thickness of the semiconductor layer, so as to thin, at least locally, the semiconductor layer by a thickness identified as being an overthickness at the end of the measurement step.