SOI Substrate Thinning With Real-Time Polishing Thickness Control
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Solution Overview
Problem
Existing methods for forming semiconductor-on-insulator (SOI) substrates face challenges in achieving uniform thickness and planarity of the semiconductor layer, which can lead to mechanical stress and cracks, affecting the reliability of the final product.
Innovation Solution
A multi-step process involving grinding and polishing operations, combined with real-time measurement and controlled feed rates, is employed to achieve uniform thickness and planarity of the semiconductor layer, using a grinding apparatus and polishing apparatus with sensing modules to monitor and adjust the polishing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single-step thinning methods are used, then the process is simple and fast, but the thickness uniformity and planarity of the semiconductor layer deteriorate
Solution Approach 1:
The thinning process is divided into multiple sequential steps: first grinding to reduce thickness, then selective etching to remove specific portions, followed by polishing to achieve final planarity. This segmentation allows each step to optimize for its specific function, resulting in superior thickness uniformity and planarity compared to single-step methods.
Solution Approach 2:
The first grinding step performs preliminary thickness reduction before the selective etching and polishing steps. This preliminary action removes the bulk of the excess thickness, reducing the workload and time required for subsequent precision steps, thereby achieving both good uniformity and reasonable process efficiency.
2Productivity
If high feed rate is used during polishing, then productivity increases, but mechanical stress and lattice strain increase causing cracks
Solution Approach 1:
The polishing process uses periodic reciprocating motion of the polishing head along the substrate surface, alternating between forward and backward strokes. This periodic action distributes the mechanical stress evenly across different regions and prevents continuous localized stress accumulation, allowing higher feed rates without causing cracks or excessive lattice strain.
3Adaptability or versatility
If non-equal indices of refraction are used for insulator and silicon layers, then optical waveguide formation is facilitated, but optical loss increases
Solution Approach 1:
The insulator layer is selectively positioned only in regions where waveguide confinement is needed, rather than uniformly across the entire substrate. This local placement allows the refractive index difference to provide waveguide formation capability where required, while minimizing the total volume of insulator material that could cause optical loss, thus balancing waveguide functionality with optical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces mechanical stress and achieves a planar semiconductor layer, enhancing the reliability and performance of the SOI substrate by minimizing lattice strain and ensuring consistent thickness across the substrate.
Implementation Method 1
a real-time measurement is conducted during the polishing of the semiconductor layer to monitor the thickness of the semiconductor layer
Implementation Method 2
reducing a thickness of the second substrate
Implementation Method 3
performing a polishing operation to reduce a thickness of the semiconductor layer
Data Source
AI summary
Methods of forming a silicon-on-insulator (SOI) substrate are provided. The methods include: forming an insulator layer on a first substrate; forming a semiconductor layer on a second substrate; bonding the semiconductor layer to the insulator layer; reducing a thickness of the second substrate; performing an etching operation to remove an entirety of the second substrate and a top portion of the semiconductor layer; and performing a polishing operation to reduce a thickness of the semiconductor layer, thereby forming a device layer having a target thickness on the insulator layer, wherein a real-time measurement is conducted during the reducing of the thickness of the semiconductor layer to monitor the thickness of the semiconductor layer while the polishing operation is being performed.