SOI Transcap Dual-Gate Tuning for CMOS Integration
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Solution Overview
Problem
Conventional semiconductor variable capacitors, such as transcaps, are limited in their ability to provide both coarse and fine capacitance tuning, which restricts their capacitance resolution and tuning range, and are incompatible with CMOS fabrication processes.
Innovation Solution
The development of semiconductor variable capacitors with separately tunable front gate and back gate capacitances, using a CMOS-compatible SOI process with a buried oxide layer, where the front gate offers coarse tuning at lower voltages and the back gate provides fine tuning at higher voltages, allowing for greater capacitance resolution and a larger tuning range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional semiconductor variable capacitors are used, then the device structure is simple, but the capacitance resolution and tuning range are limited
Solution Approach 1:
The patent divides the single capacitor structure into two separate capacitors: a first capacitor with a first control electrode and a second capacitor with a second control electrode. This segmentation allows independent control of each capacitor's capacitance, enabling both coarse and fine tuning capabilities. The first capacitor provides coarse adjustment while the second capacitor provides fine adjustment, thereby achieving high capacitance resolution and broad tuning range without excessive complexity.
Solution Approach 2:
The patent introduces a vertical stacking dimension by placing the first and second capacitors in series along the vertical axis, with the insulative layer positioned between them. This three-dimensional arrangement allows both capacitors to be integrated within a compact footprint while maintaining electrical independence through the insulative barrier, thus achieving enhanced functionality without proportional increase in planar area.
2Ease of manufacture
If conventional transcaps are used, then the device can be fabricated with simpler processes, but they are incompatible with CMOS fabrication processes
Solution Approach 1:
The patent modifies the material parameters and structural parameters of the transcap device to achieve CMOS compatibility. Specifically, the insulative layer is designed with thickness and material properties that match CMOS process requirements, and the control electrodes are structured to operate within CMOS voltage ranges. These parameter adjustments enable the device to be fabricated using standard CMOS processes while maintaining the desired capacitance tuning functionality.
3Adaptability or versatility
If a single control electrode is used, then the device structure is simpler, but the capacitance tuning range and resolution are insufficient
Solution Approach 1:
The control functionality is segmented into two independent control electrodes, each capable of independently modulating the capacitance of its associated capacitor. The first control electrode controls the first capacitor while the second control electrode controls the second capacitor. This segmentation enables differential control strategies where one electrode can provide coarse tuning and the other provides fine tuning, achieving high-resolution capacitance adjustment across a broad range.
Solution Approach 2:
The patent implements dynamic control by allowing the two control electrodes to operate with different voltage signals simultaneously. This dynamic control scheme enables the device to adapt its capacitance value in real-time with high precision, switching between coarse and fine tuning modes as needed. The independent control electrodes provide dynamic adjustability that a single control electrode cannot achieve.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables transcaps to achieve improved capacitance resolution and a broader tuning range, making them more suitable for integrated circuits while being compatible with CMOS fabrication processes.
Implementation Method 1
a first capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a first control voltage applied to the first control region
Implementation Method 2
a second capacitance between the third non-insulative region and the second non-insulative region is configured to be adjusted by varying a second control voltage applied to the second control region
Data Source
AI summary
Certain aspects of the present disclosure generally relate to a semiconductor variable capacitor offering at least two types of capacitance tuning, as well as techniques for fabricating the same. For example, a CMOS-compatible silicon on insulator (SOI) process with a buried oxide (BOX) layer may provide a transcap with a front gate (above the BOX layer) and a back gate (beneath the BOX layer). The front gate may offer lower voltage, coarse capacitance tuning, whereas the back gate may offer higher voltage, fine capacitance tuning. By offering both types of capacitance tuning, such transcaps may provide greater capacitance resolution. Several variations of transcaps with front gate and back gate tuning are illustrated and described herein.