SOI Transistor Back Gate Voltage Control via Overdoped Wells
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Solution Overview
Problem
Existing electronic chips with SOI-type MOS transistors and front and back gates face limitations in applying variable voltages between neighboring wells due to the presence of a P-N junction, which restricts the acceleration and power consumption optimization of transistors and memory cells.
Innovation Solution
The design includes separate doped wells with heavily doped back gate regions and overdoped regions under the channel-forming areas, allowing for variable voltage application between wells, with the overdoped regions enabling bidirectional charge flow and rapid potential adjustment of the back gate, and using ion implantations to form these regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a P-N junction is used between neighboring wells to enable variable voltage application, then the transistor operation speed can be accelerated, but the voltage application is restricted and power consumption optimization is limited
Solution Approach 1:
The invention extracts and eliminates the P-N junction structure between neighboring wells. By removing this junction, the patent enables independent voltage control of each well without the constraints imposed by the junction, thereby resolving the contradiction between speed acceleration and voltage application flexibility.
Solution Approach 2:
The invention segments the chip structure by providing separate biasing terminals for each well, allowing independent voltage control. This segmentation eliminates the need for P-N junctions between wells and enables versatile voltage application for optimizing both speed and power consumption.
2Reliability
If heavier doping is applied to back gate regions to improve transistor control, then the threshold voltage control is enhanced, but the manufacturing complexity increases
Solution Approach 1:
The invention applies local quality by implementing heavier doping specifically in the back gate regions beneath the channel-forming areas, while maintaining lighter doping in other well regions. This localized doping approach enhances threshold voltage control where needed without unnecessarily complicating the overall manufacturing process.
Solution Approach 2:
The patent performs preliminary doping actions during the well formation process, integrating the back gate region doping into the standard CMOS fabrication flow. This preliminary action ensures proper threshold voltage control is built into the structure from the beginning, avoiding later complex manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for the application of higher voltages between wells, enhancing the operation speed and reducing power consumption of transistors, while enabling rapid potential changes in memory cells and logic transistors, thereby overcoming the limitations imposed by the P-N junction.
Implementation Method 1
said back gate region and said overdoped region are obtained by partly overlapping ion implantations
Data Source
AI summary
An integrated circuit includes SOI-type MOS transistors on insulator, with a first well capable of being biased located under the insulator. The first wells are doped with a first conductivity type. Each first well includes, under the insulator of each transistor, a back gate region that is more heavily doped than the first well. The first wells are separated from each other by inclusion in in a second well that is also capable of being biased. The second well is doped with a second conductivity type.