SOI Transistor Buried Source Drain Fabrication
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Solution Overview
Problem
Current methods for manufacturing MOSFET transistors face challenges in simultaneously reducing the access resistance of source and drain electrodes and parasitic capacitance between the gate and source/drain, with existing solutions either complicating the fabrication process or being difficult to control effectively.
Innovation Solution
A method involving the formation of cavities in the semiconductor on insulator substrate by selective etching, followed by the deposition of an insulating film and filling with semiconductor material to create buried source and drain electrodes, which reduces parasitic capacitance and access resistance without increasing the complexity of the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the thickness of source and drain zones is increased to reduce access resistance, then access resistance decreases, but parasitic capacitance between gate and source/drain increases
Solution Approach 1:
The source and drain zones are extended vertically into the substrate below the gate level, utilizing the third dimension (depth) to reduce access resistance without increasing the lateral dimensions that would increase parasitic capacitance. This vertical extension allows current to flow through a larger cross-sectional area, reducing resistance, while the insulated gate structure prevents capacitance increase.
Solution Approach 2:
An insulating layer is introduced between the gate and the extended source/drain zones to prevent direct electrical coupling. This intermediary insulating layer eliminates the parasitic capacitance pathway while allowing the source and drain to extend close to or under the gate for resistance reduction.
2Object-generated harmful factors
If conventional methods are used to reduce parasitic capacitance, then parasitic capacitance decreases, but access resistance increases
Solution Approach 1:
Instead of reducing parasitic capacitance by increasing lateral spacing (which would increase resistance), the invention extends source and drain vertically into the substrate. This dimensional change allows simultaneous achievement of low capacitance (through insulation) and low resistance (through increased vertical cross-section).
3Object-affected harmful factors
If existing solutions are implemented to simultaneously reduce both access resistance and parasitic capacitance, then performance improves, but fabrication process complexity increases
Solution Approach 1:
The fabrication process is divided into distinct sequential steps: forming the insulating layer, creating cavities in the substrate, and filling with doped semiconductor material. This segmentation allows each step to be optimized independently and simplifies process control compared to conventional simultaneous modification approaches.
Solution Approach 2:
The insulating layer is formed in advance before cavity creation and filling. This preliminary action establishes the electrical isolation framework early in the process, enabling subsequent source/drain extension without risking parasitic capacitance formation, and simplifies later fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a reliable and precise reduction of parasitic capacitance and access resistance, enhancing the switching speed of MOSFET transistors while maintaining the integrity of the transistor structure, particularly suitable for SOI substrates with thin buried oxide layers.
Implementation Method 1
the formation of a second insulating layer, also referred to as the re-formed insulating layer, comprising the formation of an insulating film on the surfaces of the substrate bared by said etching
Implementation Method 2
the filling of the cavities by a semiconductor material so as to form the source and drain, the filling being effected preferably by at least one epitaxy
Data Source
AI summary
A method for manufacturing a transistor includes forming a stack of semiconductor on insulator type layers including at least one substrate, surmounted by a first insulating layer and an active layer to form a channel for the transistor; forming a gate stack on the active layer; producing a source and a drain including forming, on either side of the gate stack, cavities by at least one step of etching the active layer, the first insulating layer, and part of the substrate selectively to the gate stack to remove the active layer, the first insulating layer, and a portion of the substrate outside regions situated below the gate stack; forming a second insulating layer on the bared surfaces of the substrate, to form a continuous insulating layer with the first insulating layer; baring of the lateral ends of the channel; and the filling of the cavities by epitaxy.