SOI Transistor CAS Gate for Leakage and Breakdown Control
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Solution Overview
Problem
Conventional semiconductor-on-insulator FET IC structures suffer from uncontrolled secondary parasitic back-channel effects, leading to increased leakage current, lower breakdown voltage, and signal cross-coupling due to capacitive coupling with the substrate, which are not well mitigated by existing techniques like single layer transfer.
Innovation Solution
The implementation of a conductive aligned supplemental (CAS) gate structure accessed through a single layer transfer process, allowing control voltages to regulate the electrical characteristics of the primary FET adjacent to the BOX layer, replacing the uncontrolled secondary parasitic back-channel FET and providing independent control over the MOSFET.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor-on-insulator FET IC structures are used, then fabrication is simpler, but uncontrolled secondary parasitic back-channel effects occur leading to increased leakage current and lower breakdown voltage
Solution Approach 1:
The invention segments the gate control into two independent gates: a primary gate for controlling the main channel and a secondary gate for controlling the back-channel region. This segmentation allows independent optimization of each channel's electrical characteristics, enabling control over leakage current and breakdown voltage separately, thus resolving the technical contradiction between reliability and device complexity.
Solution Approach 2:
The invention introduces a dielectric layer as an intermediary between the secondary gate and the back-channel region. This dielectric mediator enables controlled capacitive coupling that allows the secondary gate to regulate the back-channel without direct contact, providing precise control over parasitic effects while maintaining electrical isolation, thereby improving breakdown voltage without excessive structural complexity.
2Ease of operation
If single layer transfer process is used, then substrate access is improved, but uncontrolled capacitive coupling with substrate persists causing signal cross-coupling
Solution Approach 1:
The invention extracts and removes the substrate from the final device structure through the single layer transfer process. By taking out the substrate entirely and replacing it with a suspended structure supported only by the BOX layer, the source of harmful capacitive coupling is eliminated, allowing substrate access during fabrication while preventing signal cross-coupling in the final device.
Solution Approach 2:
The invention transitions from a planar structure with substrate support to a three-dimensional suspended structure where the FET channel is elevated above the BOX layer. This dimensional change creates additional electrical isolation pathways and reduces parasitic coupling by separating the active channel region from potential interference sources, thereby reducing signal cross-coupling while maintaining ease of operation during fabrication.
3Power
If CAS gate structure is added, then voltage capability and control are improved, but device complexity increases
Solution Approach 1:
The secondary gate structure serves multiple functions simultaneously: it controls the back-channel region to reduce leakage current, enhances the breakdown voltage capability, and provides an additional control terminal for optimizing device performance. By making the secondary gate multi-functional, the invention achieves improved voltage capability without proportionally increasing device complexity, as a single structural addition addresses multiple performance requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher voltage capability, lower ON resistance, and reduced leakage currents in subthreshold operating conditions by biasing the CAS gate, improving the overall performance of FETs without increasing heat generation, and allowing for varying threshold voltages through different bias voltages.
Implementation Method 1
a conductive aligned supplemental (CAS) gate, fabricated in relation to a second, opposite side of the insulator layer and aligned with at least a portion of the primary FET, such that the source S, the drain D, the CAS gate, and at least the insulator layer function as a field effect transistor
Implementation Method 2
a body B, defined below the gate G, between the source S and the drain D; an insulator layer; a conductive aligned supplemental (CAS) gate, fabricated in relation to a second, opposite side of the insulator layer
Data Source
AI summary
Semiconductor-on-insulator field effect transistor (FET) integrated circuit (IC) structures and fabrication processes that mitigate or eliminate the problems caused by the secondary parasitic back-channel FET of conventional semiconductor-on-insulator FET IC structures. Embodiments enable full control of the secondary parasitic back-channel FET of semiconductor-on-insulator IC primary FETs. Embodiments include taking partially fabricated ICs made using a process which allows access to the back side of the FET, such as “single layer transfer” process, and then fabricating a conductive aligned supplemental (CAS) gate structure relative to the insulating layer juxtaposed to a primary FET such that a control voltage applied to the CAS gate can regulate the electrical characteristics of the regions of the primary FET adjacent the insulating layer. The IC structures present as a four or five terminal device: source S, drain D, primary gate G, CAS gate, and, optionally, a body contact.