SOI Transistor Channel Last Epitaxy Reduces Access Resistance
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Solution Overview
Problem
Fully depleted silicon-on-insulator (SOI) transistors face challenges due to random doping fluctuations and variability in threshold voltages, which affect integrated circuit yield and performance, particularly with the use of thin silicon films leading to parasitic series resistance and limited source and drain conductance.
Innovation Solution
The implementation of a 'Channel Last' process for SOI transistors, where a low-temperature epitaxial channel is formed in a recessed region with a δ-layer for precise threshold voltage control and a thicker active channel, reducing random variability and enhancing source and drain conductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thin silicon films are used in fully depleted SOI transistors, then threshold voltage control is improved and random doping fluctuations are reduced, but parasitic series resistance increases and source/drain conductance is limited
Solution Approach 1:
The channel region is segmented into multiple thin silicon layers separated by buried oxide layers, creating a stacked structure. This segmentation allows each layer to be fully depleted for precise threshold control while the cumulative thickness provides sufficient conductance. The multi-layer structure divides the electrical conduction path through multiple interfaces, reducing parasitic resistance in each individual layer while maintaining overall threshold voltage precision.
Solution Approach 2:
The transistor structure uses a composite of silicon layers and buried oxide layers to create a multi-layer channel. The silicon provides conductive pathways while the buried oxide layers provide electrical isolation and enable full depletion. This composite structure combines the benefits of thin silicon (precise threshold control) with sufficient total thickness (reduced parasitic resistance) by stacking multiple such combinations.
2Reliability
If silicon film thickness is increased to reduce parasitic resistance, then source and drain conductance improve, but random doping fluctuations and threshold voltage variability increase
Solution Approach 1:
Instead of using a single thick silicon layer, the structure segments the channel into multiple thin silicon layers separated by buried oxide. Each thin layer maintains full depletion for precise threshold control, while the stacked configuration provides sufficient total conductance. This segmentation resolves the contradiction by achieving both thin-layer precision and thick-layer conductance.
Solution Approach 2:
The solution transitions from a single-dimensional thick silicon layer to a multi-dimensional stacked structure of thin layers separated by oxide. This dimensional change allows the effective channel thickness to be increased (reducing parasitic resistance) while maintaining thin individual layer thickness (preserving threshold control precision) by utilizing the vertical stacking dimension.
3Ease of manufacture
If conventional SOI structures are used, then manufacturing is simpler, but threshold voltage uncertainty and random variability adversely affect integrated circuit yield
Solution Approach 1:
The channel is segmented into multiple identical thin silicon layers separated by buried oxide layers. This segmentation allows the use of standard thin-film fabrication processes for each layer while the stacked configuration provides cumulative benefits. The repetitive structure simplifies manufacturing by using identical process steps for each layer, yet achieves reduced threshold variability through the multi-layer architecture.
Solution Approach 2:
The invention changes the parameter of silicon layer thickness from thick (conventional) to thin (multiple layers), and changes the structural parameter from single-layer to multi-layer stacked configuration. This parameter change maintains compatibility with standard fabrication processes while fundamentally improving threshold voltage control by ensuring full depletion in each thin layer, reducing random doping fluctuations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces threshold voltage uncertainty, improves access resistance, and increases drive current by allowing thicker silicon films and precise threshold voltage tuning, addressing both doping and junction location variability issues.
Implementation Method 1
a low-temperature epitaxial channel is formed in a recessed region
Implementation Method 2
a δ-layer for precise threshold voltage control
Data Source
AI summary
The structure, and fabrication method thereof, implements a fully depleted silicon-on-insulator (SOI) transistor using a “Channel Last” procedure in which the active channel is a low-temperature epitaxial layer in an etched recess in the SOI silicon film. An optional δ-layer of extremely high doping allows its threshold voltage to be set to a desired value. Based on high-K metal gate last technology, this transistor has reduced threshold uncertainty and superior source and drain conductance. The use of epitaxial layer improves the thickness control of the active channel and reduces the process induced variations. The utilization of active silicon layer that is two or more times thicker than those used in conventional fully depleted SOI devices, reduces the access resistance and improves the on-current of the SOI transistor.