SOI Transistor Epi Volume via Buried Insulation Recesses
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Solution Overview
Problem
In the fabrication of integrated circuits, the epitaxial semiconductor material in the source/drain regions of transistors on a semiconductor-on-insulator (SOI) substrate often relaxes due to subsequent processing operations, reducing the desirable stress on the channel region and impairing transistor performance.
Innovation Solution
The method involves forming a plurality of distinct openings through the active semiconductor layer in the source/drain region, extending to recesses in the buried insulation layer, where epitaxial semiconductor material is deposited, both within these openings and over the surface of the active semiconductor layer, thereby increasing the epi volume and maintaining stress on the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial semiconductor material is grown on the active semiconductor layer in the source/drain regions, then stress is imparted to the channel region, but subsequent processing operations cause the epi material to relax, reducing the stress and transistor performance
Solution Approach 1:
The patent embeds the epitaxial semiconductor material within recesses formed in the buried insulation layer, effectively nesting the epi material inside a cavity structure. This nesting approach anchors the epi material to the substrate through sidewall contact, preventing relaxation during subsequent processing operations while maintaining the stress imparted to the channel region
Solution Approach 2:
The patent performs preliminary etching to form recesses in the buried insulation layer before depositing the epitaxial semiconductor material. This preliminary action creates a structural foundation that prevents subsequent relaxation, ensuring the epi material maintains its stress-giving properties throughout later processing steps
2Stress or pressure
If more epitaxial semiconductor material is positioned adjacent the channel region to increase epi volume, then stress on the channel region is enhanced, but the epi material relaxes during processing, reducing the desired stress levels
Solution Approach 1:
By nesting the epi material within recesses that extend into the buried insulation layer, the patent creates sidewall contact that mechanically anchors the material. This prevents relaxation even as the epi volume increases, allowing enhanced stress on the channel region to be maintained throughout processing
Solution Approach 2:
The patent extends the epi material volume not only laterally adjacent to the channel region but also vertically into the recesses of the buried insulation layer. This three-dimensional positioning increases the epi volume and stress-giving capability while the recess structure prevents relaxation
3Volume of stationary object
If recesses are formed in the active semiconductor layer to expose the buried insulation layer, then more epi material can be positioned adjacent the channel region, but processing operations after epi formation still cause relaxation
Solution Approach 1:
The patent forms recesses that extend through the active semiconductor layer into the buried insulation layer, creating cavities where epi material can be deposited. The epi material is nested within these recesses, with sidewalls providing mechanical anchoring that prevents relaxation during subsequent processing
Solution Approach 2:
The recesses are formed in advance before epi material deposition, creating a pre-prepared structure that prevents relaxation. This preliminary formation of recesses into the buried insulation layer ensures that when epi material is added, it is immediately anchored and cannot relax during later processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the stress imparted to the channel region, improving transistor performance by reducing source-to-drain resistance and maintaining the desired stress levels, leading to increased drain current and improved AC performance.
Implementation Method 1
an epitaxial (epi) semiconductor material disposed in the recesses in the BOX layer, in the plurality of openings through the active semiconductor layer, and over a surface of the active semiconductor layer
Data Source
AI summary
A transistor device formed on a semiconductor-on-insulator (SOI) substrate including a bulk semiconductor layer, a buried insulation (BOX) layer positioned on the bulk semiconductor layer, and an active semiconductor layer positioned on the BOX layer. The transistor device includes: a gate structure, a sidewall spacer, and a source/drain region; a plurality of distinct openings extending through the active semiconductor layer of the SOI substrate in the source/drain region adjacent the sidewall spacer, each opening of the plurality of openings extending to a respective recess formed in the BOX layer of the SOI substrate in the source/drain region adjacent the sidewall space, wherein each recess extends under a portion of the active semiconductor layer; and an epitaxial (epi) semiconductor material disposed in the recesses in the BOX layer, in the plurality of openings through the active semiconductor layer, and over a surface of the active semiconductor layer.