SOI Transistor RF Isolation via Field Control Ring
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Solution Overview
Problem
Capacitive coupling between source/drain regions and the underlying bulk silicon substrate in SOI transistors affects RF signal isolation, leading to reduced resistivity and increased RF coupling, which is not adequately addressed by existing methods such as increasing buried oxide layer thickness or using high-resistivity sapphire substrates due to manufacturing cost concerns and induced surface conducting layers.
Innovation Solution
A field control ring is introduced to control surface conductivity in the bulk substrate by applying an electrical charge, limiting the conductive surface layer to the portion underlying the SOI transistor, thereby increasing the overall resistivity and reducing RF coupling by isolating the conductive surface layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the thickness of the buried oxide layer is increased to reduce capacitive coupling, then RF signal isolation is improved, but strain in the SOI substrate increases causing wafer warping
Solution Approach 1:
The patent changes the electrical parameter (resistivity) of the bulk silicon substrate from conventional low resistivity to high resistivity (greater than 1000 ohm-cm). This parameter change reduces the conductivity of the bulk substrate, thereby reducing capacitive coupling and RF signal leakage to ground without requiring increased buried oxide thickness, thus avoiding wafer warping issues
Solution Approach 2:
The patent uses a high-resistivity bulk silicon substrate as a cost-effective alternative to expensive sapphire substrates. While high-resistivity silicon has limitations (surface conducting layers), it provides a practical, manufacturable solution that balances performance and cost without the extreme measures of thick buried oxide or sapphire
2Object-affected harmful factors
If a high-resistivity bulk silicon substrate is used to reduce capacitive coupling, then RF signal isolation is improved, but trapped charge induces surface charge forming a conducting layer that reduces overall resistivity
Solution Approach 1:
The patent introduces a thin film insulator layer as an intermediary between the high-resistivity bulk silicon substrate and the SOI transistor structures. This intermediate layer prevents charge trapping and surface charge formation at the silicon-silicon dioxide interface, eliminating the mechanism that creates unwanted conducting layers while preserving the high-resistivity benefits
Solution Approach 2:
The patent uses a thin film insulator that replicates the beneficial electrical isolation properties of thicker buried oxide structures but with superior charge retention characteristics. The thin film insulator copy provides the same isolation function without the charge trapping defects of conventional thick buried oxide approaches
3Object-affected harmful factors
If a sapphire substrate is used instead of bulk silicon to reduce capacitive coupling, then RF signal isolation is improved, but manufacturing cost significantly increases
Solution Approach 1:
The patent replaces expensive sapphire substrates with high-resistivity bulk silicon substrates, which are significantly cheaper and more compatible with existing CMOS manufacturing processes. This substitution maintains adequate RF isolation performance while dramatically reducing material and processing costs
Solution Approach 2:
The patent changes the substrate material parameter from sapphire to high-resistivity silicon, and further optimizes by adding a thin film insulator layer. This parameter change achieves comparable or superior electrical isolation to sapphire while maintaining compatibility with standard silicon fabrication processes, reducing manufacturing complexity and cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The field control ring effectively minimizes RF coupling between SOI transistors and ground, enhancing RF performance by increasing the resistance of the bulk substrate and preventing unwanted signal paths between transistors.
Implementation Method 1
A field control ring is introduced to control surface conductivity in the bulk substrate by applying an electrical charge
Implementation Method 2
increasing the overall resistivity and reducing RF coupling by isolating the conductive surface layer
Data Source
AI summary
According to one example embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the buried oxide layer overlies a bulk substrate. The structure further includes an electrically charged field control ring situated over the buried oxide layer and surrounding the at least one SOI transistor. A width of the electrically charged field control ring is greater than a thickness of the buried oxide layer. The electrically charged field control ring reduces a conductivity of a surface portion of the bulk substrate underlying the field control ring, thereby reducing RF coupling of the at least one SOI transistor through the bulk substrate. The structure further includes an isolation region situated between the electrically charged field control ring and the at least one SOI transistor. A method to achieve and implement the disclosed structure is also provided.