SOI Transistor Body Grooves for Charge Storage and Punch-Through Prevention
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Solution Overview
Problem
Conventional SOI devices face reduced charge storage capacity and operational issues due to the punch-through phenomenon caused by deep junction regions and the need for high dose ion implantation, which degrades transistor performance as device size decreases.
Innovation Solution
The SOI device features a substrate with grooves extending from the upper silicon layer to a partial depth of the buried oxide layer, filled with an epi-silicon layer and an insulation oxide layer, allowing junction regions to contact the insulation layer instead of the buried oxide, thereby increasing transistor body volume and preventing punch-through.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of cells is decreased to accommodate more highly integrated semiconductor devices, then the integration density is improved, but the charge storage capacity of the bodies degrades
Solution Approach 1:
The invention divides the body region into two parts: a first body region with a first doping concentration and a second body region with a second doping concentration. This segmentation allows the first body region to provide charge storage capacity while the second body region maintains transistor operation, resolving the contradiction between small cell size and sufficient charge storage.
Solution Approach 2:
Different regions of the body are doped with different concentrations locally. The first body region has a first doping concentration optimized for charge storage, while the second body region has a second doping concentration optimized for transistor operation. This local quality differentiation allows each region to fulfill its specific function despite the overall small cell size.
2Reliability
If high dose ion implantation is implemented to form junction regions sufficiently deep to contact the buried oxide layer, then the floated body structure is achieved, but the volume of junction regions increases causing punch-through phenomenon
Solution Approach 1:
The invention applies different doping concentrations to different regions: the first body region has a first doping concentration that allows junction regions to contact the buried oxide layer and form floated bodies, while the second body region has a second doping concentration that prevents punch-through. This local quality differentiation resolves the contradiction between achieving floated body structure and preventing punch-through.
Solution Approach 2:
The body is segmented into a first body region for forming junction regions that contact the buried oxide layer, and a second body region that prevents punch-through. This segmentation allows the junction regions to be sufficiently deep for floated body formation without causing punch-through in the transistor channel region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances charge storage capacity and prevents punch-through, improving transistor operation characteristics by increasing the volume of transistor bodies and reducing the depth required for junction regions, leading to increased charge storage and improved operational performance.
Implementation Method 1
a second silicon layer formed to fill the grooves which have the insulation layer formed therein
Implementation Method 2
The insulation layer comprises an oxide layer
Data Source
AI summary
An SOI device includes an SOI substrate having a stacked structure including a buried oxide layer and a first silicon layer sequentially stacked on a silicon substrate. The SOI substrate possesses grooves having a depth that extends from an upper surface of the first silicon layer to a partial depth of the buried oxide layer. An insulation layer is formed on the lower surfaces of the grooves and a second silicon layer is formed filling the grooves having the insulation layer formed thereon. Gates are formed on the second silicon layer and junction regions are formed in the first silicon layer on both sides of the gates to contact the insulation layer.