SOI High-Voltage Transistor Epitaxy for Hot Carrier Control

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Solution Overview

Problem

High-voltage transistors manufactured on silicon-on-insulator (SOI) bulk suffer from hot carrier injection, leading to performance degradation, and the conventional addition of a monolithic bulk region limits the 'fully depleted' and 'partially depleted' effects, affecting short channel control and transistor characteristics.

Innovation Solution

The method involves epitaxially growing a semiconductor film to a greater thickness only in the high-voltage region of the SOI bulk, electrically insulated by a buried dielectric layer, to avoid hot carrier injection while maintaining performance advantages, by controlling the film thickness independently of other epitaxy steps and achieving a fully depleted state.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the semiconductor film thickness is increased to prevent hot carrier injection, then the reliability of high-voltage transistors is improved, but the performance advantages of SOI devices (fully depleted effect) are lost

Engineering Contradiction:
Improvetransistor reliabilityVSAvoidshort channel control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating a localized monolithic bulk region with increased semiconductor film thickness specifically in the high-voltage transistor area, while maintaining the original thin SOI film thickness in other regions. This is achieved through selective epitaxial growth masked by a hard mask layer, allowing the high-voltage transistors to benefit from improved reliability without compromising the overall SOI device performance and short channel control in other regions.

Inventive Principle:
Principle #3Local quality

2Reliability

If a localized monolithic bulk region is added to manufacture high-voltage transistors, then hot carrier injection is limited, but the device complexity increases

Engineering Contradiction:
Improvetransistor reliabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the formation of the localized monolithic bulk region with the existing SOI manufacturing process by integrating selective epitaxial growth into the standard process flow. The selective epitaxial growth step is combined with hard mask formation and removal steps that are already part of the manufacturing sequence, allowing the complex structural modification to be achieved without adding significant process complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If the semiconductor film is made thicker in the high-voltage region, then hot carrier injection is prevented, but the electrostatic control and short channel effects are degraded

Engineering Contradiction:
Improvetransistor reliabilityVSAvoidshort channel control
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent resolves this contradiction by applying local quality - the semiconductor film thickness is increased only in the specific high-voltage region where hot carrier injection occurs, while maintaining the thin film structure in other regions. The selective epitaxial growth with hard mask patterning ensures that the thickness modification is localized precisely to the high-voltage transistor channels, preserving electrostatic control and short channel effects in non-high-voltage areas.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability and performance of high-voltage transistors by preventing hot carrier injection and ensuring better electrostatic control, reducing short channel effects, and allowing operation at higher voltages without degrading performance.

Implementation Method 1

A method embodiment may include epitaxially growing the semiconductor film to a second thickness greater than the first thickness, selectively in the high-voltage region.

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS20240014215A1Method for manufacturing high-voltage transistors on a silicon-on-insulator type bulk
Publication Date: 2024.01.11 STMICROELECTRONICS (CROLLES 2) SAS
  • US20240014215A1 patent drawing
  • US20240014215A1 patent drawing
  • US20240014215A1 patent drawing

AI summary

A method can be used for manufacturing a high-voltage transistor in and on a high-voltage region of a silicon-on-insulator type bulk that includes a semiconductor film having a first thickness, electrically insulated from a carrier bulk by a buried dielectric layer. The semiconductor film in the high-voltage region is selectively epitaxially grown to a second thickness that is greater than the first thickness while the semiconductor film remains at the first thickness in a region outside the high-voltage region.