SOI Transistor Contact Layout for Leakage Isolation
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Solution Overview
Problem
High integration of transistors in semiconductor devices leads to increased leakage current between adjacent transistors, making it difficult to reduce the pitch between elements and resulting in a higher ratio of transistor to chip area, particularly in withstand voltage transistors like memory block select transistors, which complicates manufacturing and increases the risk of latch-up.
Innovation Solution
Transistors are formed on an insulating layer separated from the semiconductor substrate, reducing leakage between adjacent transistors and allowing for a smaller pitch, and the insulating layer is used to apply high voltages and prevent inversion layers, simplifying the manufacturing process and improving back bias characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistors are formed directly on the semiconductor substrate to achieve high integration, then the transistor-to-chip area ratio improves, but leakage current between adjacent transistors increases
Solution Approach 1:
The semiconductor substrate is segmented into multiple isolated regions by insulating layers, with each region containing transistors. This segmentation physically separates adjacent transistor regions, preventing leakage current while maintaining high integration density. The insulating layers create distinct isolated regions that can be independently controlled.
Solution Approach 2:
Insulating layers are introduced as intermediary elements between the semiconductor substrate and the transistor regions. These intermediary layers prevent direct electrical interaction between adjacent transistor regions, thereby eliminating leakage current paths while allowing the transistors to function independently.
2Productivity
If pitch between elements is reduced to increase integration density, then chip area utilization improves, but leakage current between adjacent transistors increases
Solution Approach 1:
The substrate is divided into multiple isolated regions separated by insulating layers, allowing elements within each region to be closely spaced while preventing leakage between regions. This segmentation enables high integration density without the leakage problems that would result from reducing pitch in continuous substrate structures.
3Reliability
If triple well structures are used to prevent latch-up, then reliability improves, but manufacturing complexity increases
Solution Approach 1:
The invention extracts and removes the complex triple well structure requirement by using insulating layers to isolate transistor regions. Instead of implementing the complicated triple well doping structure, the patent uses simpler insulating layer formation to achieve the same latch-up prevention effect, thereby reducing manufacturing complexity.
Solution Approach 2:
Insulating layers serve as intermediary structures that prevent latch-up by electrically isolating adjacent transistor regions. This intermediary approach replaces the need for complex triple well structures, achieving reliable latch-up prevention through a simpler manufacturing process.
Data Source
AI summary
Embodiments provide a semiconductor device capable of being highly integrated.A semiconductor device includes a semiconductor substrate, a first insulating layer formed toward an inside of a semiconductor substrate from a main surface of the semiconductor substrate, and a transistor formed on the first insulating layer. the transistor has a first semiconductor layer formed on the first insulating layer to be insulated from the semiconductor substrate, a second insulating layer provided on a second region among of a first region, the second region, and a third region sequentially arranged in a first direction along the main surface of the first semiconductor layer, and a first conductive layer provided on the second insulating layer. a first contact is connected to the first region of the first semiconductor layer, a second contact is connected to the third region of the first semiconductor layer, and a third contact is connected to the first conductive layer.