SOI Transistor Isolation via Localized Etching
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Solution Overview
Problem
The production of electrical insulation between transistors on a silicon on insulator (SOI) substrate, particularly in fully depleted SOI (FDSOI) technology, faces challenges due to the increasing complexity of photolithography in creating shallow trenches for transistors of the same conductivity type, as the space between active zones becomes smaller.
Innovation Solution
A method that forms electrical insulation between semiconductor domains after the formation of gate regions, using localized etching and filling with insulating material, eliminating the need for shallow trenches and reducing photolithographic constraints, while protecting specific areas with resin blocks to prevent unwanted epitaxy formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trenches are produced by photolithography to insulate transistors of the same conductivity type, then electrical insulation between transistor domains is achieved, but photolithographic complexity increases as space between active zones decreases
Solution Approach 1:
The patent applies preliminary action by forming the gate regions and dummy gate regions before creating the insulation structures. The method performs localized etching of the semiconductor film between dummy gate regions down to the buried insulating layer, then fills with insulating material. This sequence eliminates the need for photolithography-defined shallow trenches, as the insulation structures are formed after gate patterning using simpler etching and deposition processes.
2Reliability
If shallow trenches are produced by photolithography to insulate transistors, then electrical insulation is achieved, but manufacturing precision becomes more difficult as trench dimensions shrink
Solution Approach 1:
The patent replaces the photolithography-based mechanical trench formation with a chemical etching process. Instead of using photolithography to define and etch shallow trenches, the method uses localized etching of the semiconductor film between dummy gate regions, followed by filling with insulating material. This substitution of etching and deposition for photolithography-based trench formation improves manufacturing precision by avoiding the resolution limits and complexity of photolithographic patterning at small dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the insulation process, reduces photolithographic complexity, and effectively creates electrical insulation between transistors of the same conductivity type without the need for shallow trenches, enhancing the precision and efficiency of transistor production on SOI substrates.
Implementation Method 1
performing a localized etching of a first part of the semiconductor film between two first dummy gate regions down to the buried insulating layer
Implementation Method 2
the first etched part of the semiconductor film may be filled by at least one insulating material (e.g., a dielectric such as PMD ('PreMetal Dielectric')) to thereby form the two domains of the semiconductor film electrically insulated from one another
Implementation Method 3
Production by photolithography of this overlapping block of resin may therefore be less constraining than a photolithography step used in prior approaches to produce the shallow trenches
Implementation Method 4
A first epitaxy of a first semiconductor material may be formed on the first zone of the semiconductor film between the first patterns, except for the first part of the semiconductor film covered by the at least one insulating layer
Data Source
AI summary
An integrated circuit may include an SOI substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first MOS transistors and also first dummy gate regions. The first zone may include two domains having a space therebetween, and the space may be filled by at least one insulating material and be situated between two dummy gate regions above a region of the supporting substrate without any insulating trench.