Body-Contacted SOI Transistor Segmented Contact Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Body-contacted SOI transistors face significant circuit loading capacitance and increased resistance issues as gate width increases, leading to improper body tying in high current applications, necessitating an improved design for effective electrical contact.
Innovation Solution
The formation of body-contacted semiconductor-on-insulator (SOI) transistors with first and second active regions of different heights and conductivity types, along with a polysilicon gate, allows for improved electrical contact by using a p-type implant and siliciding to reduce resistance and capacitance, enabling better body tying.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate width is increased to handle high current applications, then the current handling capability is improved, but the resistance along the body to the body contact increases
Solution Approach 1:
The body contact structure is segmented into multiple regions: a first body contact region directly contacting the substrate, and a second body contact region extending under the gate. This segmentation allows different portions of the body to be contacted at different locations, reducing the resistance along the body path while maintaining proper body tying for high current applications
Solution Approach 2:
The body contact is extended into a third dimension by creating a body contact region that extends underneath the gate structure. This vertical extension provides an additional conduction path for body potential, reducing the resistance along the body without requiring increased gate width
2Device complexity
If a polysilicon gate is used to separate source/drain regions from the body contact region, then the transistor structure is simplified, but the circuit loading capacitance increases substantially
Solution Approach 1:
The harmful capacitive coupling between the gate and body contact is extracted by introducing a pinned diode structure that provides a low-impedance path to ground. This removes the unwanted capacitance effect while preserving the beneficial gate separation function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced resistance and capacitance, ensuring proper electrical contact and improved operation of SOI transistors, particularly in high current applications by effectively tying the body and source regions.
Implementation Method 1
a p-type implant and siliciding to reduce resistance and capacitance
Implementation Method 2
a p-type implant and siliciding to reduce resistance and capacitance
Data Source
AI summary
A method for making a semiconductor device includes patterning a semiconductor layer, overlying an insulator layer, to create a first active region and a second active region, wherein the first active region is of a different height from the second active region, and wherein at least a portion of the first active region has a first conductivity type and at least a portion of the second active region has a second conductivity type different from the first conductivity type in at least a channel region of the semiconductor device. The method further includes forming a gate structure over at least a portion of the first active region and the second active region. The method further includes removing a portion of the second active region on one side of the semiconductor device.