SOI Transistor Electrical Connection via Segmented Paths
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Solution Overview
Problem
In semiconductor devices with a silicon-on-insulator (SOI) structure, existing techniques for establishing electrical connection from the front surface to the substrate can lead to transistor characteristic variations and degradation of the gate oxide layer due to charge accumulation and bias-induced charging issues.
Innovation Solution
A semiconductor device structure and manufacturing method involving through holes filled with conductors, forming electrodes connected to both the transistors and conductors, and using interlayer insulating layers to establish electrical connections between the gate electrode, device isolating regions, and the support substrate, thereby preventing charge accumulation and stabilizing the transistor potential.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrical connection is established from the front surface of the IC to the substrate through contact holes in the buried oxide layer, then electrical connection is achieved, but charge accumulation occurs and transistor characteristics vary
Solution Approach 1:
The invention divides the electrical connection path into two separate segments: one for signal transmission (through the buried oxide layer to the substrate) and another for charge dissipation (through the device isolating region to the substrate). This segmentation prevents charge accumulation in the transistor channel while maintaining necessary electrical connections, thereby resolving the contradiction between achieving electrical connection and avoiding harmful charge effects.
2Stability of the object's composition
If the substrate potential is fixed through conventional bonding techniques, then potential stabilization is achieved, but charge from CVD or etching processes accumulates on the substrate
Solution Approach 1:
The invention introduces a dedicated charge dissipation path that acts as an intermediary mechanism between the substrate and the charging processes. This separate path allows charges generated during CVD or etching to be safely dissipated to the substrate without affecting the potential stability achieved through conventional bonding, thus resolving the contradiction between potential stabilization and charge accumulation prevention.
3Ease of manufacture
If contact holes are formed through the buried oxide layer for electrical connection, then substrate connection is established, but gate oxide layer degradation occurs due to bias-induced charging
Solution Approach 1:
The invention segments the electrical connection function into two distinct paths: one for signal transmission through the buried oxide layer and another for charge management through the device isolating region. This segmentation prevents bias-induced charging from degrading the gate oxide layer while maintaining ease of manufacture through standard contact hole formation processes.
Data Source
AI summary
There is provided a semiconductor device in which the characteristic variations of a transistor and the degradation of a gate oxide layer are reduced during a WP process and a method for manufacturing the same. The semiconductor device includes a semiconductor chip having an SOI transistor. The SOI transistor includes a semiconductor layer comprising device isolating regions, a channel region, and diffusion regions that sandwich the channel region therebetween. The semiconductor layer is formed on a support substrate via a first insulating layer. A gate electrode is formed on the channel region of the semiconductor layer via a second insulating layer. The semiconductor chip has, on the first surface, a first electrode pad electrically connected to the SOI transistor and a second electrode pad electrically connected to the support substrate.