SOI Field-Effect Transistor Stress Layout for Mobility Gain
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Solution Overview
Problem
Existing semiconductor devices, particularly field-effect transistors (FETs) built on bulk substrates, face limitations in enhancing charge carrier mobility, which can be addressed by introducing stress to the channel region, but there is a need for further device improvements to meet industry demands.
Innovation Solution
The introduction of stress-inducing components, including semiconductor structures and dielectric components, is achieved by forming a semiconductor-on-insulator (SOI) substrate with specific arrangements and materials to induce tensile or compressive stress on the channel region of n-type and p-type FETs, respectively, using epitaxially-grown materials and strained dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If stress-inducing components are introduced to enhance charge carrier mobility, then device speed and performance improve, but device structure and fabrication complexity increase
Solution Approach 1:
The stress-inducing component is divided into multiple dielectric portions positioned at different locations (first portion adjacent to source/drain regions, second portion under the gate structure) to independently induce stress in different channel regions. This segmentation allows targeted stress application to optimize charge carrier mobility in n-type and p-type FETs separately while maintaining manageable structural complexity
Solution Approach 2:
The dielectric component serves multiple functions: it provides electrical isolation, induces tensile stress in n-type FET channel regions adjacent to source/drain, induces compressive stress in p-type FET channel regions, and maintains structural integrity. This multi-functionality reduces the need for additional separate components, thereby limiting the increase in device complexity
2Reliability
If stress-inducing components are introduced to enhance charge carrier mobility, then charge carrier mobility improves, but manufacturing process complexity increases
Solution Approach 1:
The dielectric component is formed in the insulator layer before the gate structure is assembled, allowing stress to be pre-induced in the channel region during subsequent processing steps. This preliminary placement ensures that stress is already present when the gate is formed, eliminating the need for additional post-fabrication stress application steps
Solution Approach 2:
The dielectric component utilizes material property differences (elastic modulus, thermal expansion coefficient) between the dielectric material and surrounding structures to induce stress. By selecting appropriate dielectric materials with specific physical parameters, the desired tensile or compressive stress is automatically generated during thermal processing or deposition, simplifying the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances charge carrier mobility, leading to improved device performance and efficiency in semiconductor-on-insulator field-effect transistors.
Implementation Method 1
introducing stress to a channel region between a source region and a drain region thereof to increase charge carrier mobility
Implementation Method 2
using epitaxially-grown materials and strained dielectric materials
Data Source
AI summary
A transistor is provided. The transistor includes a substrate, a gate structure, a semiconductor structure, and a dielectric component. The gate structure is over the substrate and the semiconductor structure is adjacent to the gate structure. The semiconductor structure has a first side facing the gate structure and a second side laterally opposite the first side. The dielectric component is in the substrate. The dielectric component has a first portion adjacent to the second side of the semiconductor structure and a second portion under the first portion, wherein the second portion extends under the gate structure.