SOI Transistor Threshold Voltage Control via Ultra-Shallow Junction Doping
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Solution Overview
Problem
Conventional silicon-on-insulator (SOI) MOSFETs face challenges in maintaining consistent threshold voltage due to random dopant fluctuations, especially as critical dimensions shrink, leading to undesirable variations in threshold voltage and reduced mobility and transconductance.
Innovation Solution
The improved SOI transistor design features a substantially undoped channel with a highly doped screening region and a threshold voltage set region, allowing for precise control of threshold voltage without the use of pocket or halo implants, using epitaxially-grown silicon and dopant migration resistant layers to minimize dopant migration and variability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dopants are implanted into the channel to adjust threshold voltage, then threshold voltage can be controlled, but random dopant fluctuations cause threshold voltage variation
Solution Approach 1:
The patent changes the doping parameter from conventional channel doping to ultra-shallow junction doping with peak concentration greater than 1×10^20 atoms/cm³ and depth less than 10 nm. This parameter change allows precise threshold voltage control while minimizing random dopant fluctuations that cause variation, as the dopants are confined to a very shallow region beneath the gate oxide interface.
Solution Approach 2:
The patent transitions from planar channel doping to vertical ultra-shallow junction doping beneath the gate oxide. By moving the dopant placement to a different spatial dimension (ultra-shallow depth below the interface), the invention achieves precise threshold voltage control without the lateral spread that causes random dopant fluctuations in conventional approaches.
2Productivity
If critical dimensions are shrunk to improve device scaling, then device density increases, but dopant fluctuations have greater impact on threshold voltage
Solution Approach 1:
The patent employs ultra-shallow junction parameters with peak dopant concentration >1×10^20 atoms/cm³ and depth <10 nm, which maintains effective doping for threshold voltage control even in scaled devices. This parameter regime ensures that random dopant fluctuations remain minimal despite reduced device dimensions, enabling continued scaling without proportional increases in threshold voltage variation.
3Measurement precision
If halo implants are used to adjust threshold voltage, then threshold voltage can be modified, but manufacturing complexity increases
Solution Approach 1:
The patent extracts the threshold voltage control function from complex multi-step halo implant processes and consolidates it into a single ultra-shallow junction doping step. By taking out the unnecessary complexity of halo implants and retaining only the essential doping function performed at ultra-shallow depths, the invention achieves threshold voltage adjustment with simplified manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable setting of threshold voltage, improved mobility, transconductance, and reduced junction capacitance, allowing for scalable voltage settings and reduced manufacturing costs by eliminating the need for halo implants, thereby enhancing the performance and consistency of SOI transistors.
Implementation Method 1
using epitaxially-grown silicon and dopant migration resistant layers to minimize dopant migration and variability
Implementation Method 2
dopant migration resistant layers to minimize dopant migration and variability
Data Source
AI summary
A field effect transistor having a source, drain, and a gate can include a semiconductor substrate, a buried insulator layer positioned on the semiconductor substrate, and a semiconductor overlayer positioned on the buried insulator layer; a low dopant channel region positioned below the gate and between the source and the drain and in an upper portion of the semiconductor overlayer; and a plurality of doped regions having a predetermined dopant concentration profile, including a screening region positioned in the semiconductor overlayer below the low dopant channel region, the screening region extending toward the buried insulator layer, and a threshold voltage set region positioned between the screening region and the low dopant channel, the screening region and the threshold voltage set region having each a peak dopant concentration, the threshold voltage region peak dopant concentration being between 1/50 and ½ of the peak dopant concentration of the screening region.