SOI Deep Trench Isolation With Bottom Dielectric Charge Balancing
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Solution Overview
Problem
Deep trench semiconductor structures, particularly in silicon-on-insulator (SOI) transistors, are susceptible to process charging damage due to unbalanced voltage between the substrate and gate, leading to gate oxide damage, which existing methods fail to adequately address.
Innovation Solution
A dielectric layer is formed at the bottom of deep trenches to isolate polysilicon from the substrate silicon, comprising multiple sub-layers of silicon oxide, with specific thickness ranges to prevent excessive heat dissipation and inductive charge, thereby reducing unbalanced voltage and process charging damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep trenches are formed in SOI substrate to create bipolar devices, then device performance is improved, but process charging damage occurs due to unbalanced voltage between substrate and gate
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the polysilicon gate and the silicon substrate in deep trench regions. This dielectric layer acts as a mediator that prevents direct charge coupling, thereby eliminating the unbalanced voltage condition that causes process charging damage while allowing the deep trench bipolar device performance to be maintained
2Object-affected harmful factors
If dielectric layer thickness is increased to prevent inductive charge, then process charging damage is reduced, but heat dissipation capability deteriorates
Solution Approach 1:
The dielectric layer thickness is optimized to a specific range (500-1000 Å) that balances two opposing requirements: it is thick enough to effectively prevent inductive charge and process charging damage, yet thin enough to maintain adequate heat dissipation capability. This parameter optimization resolves the contradiction between charge isolation and thermal management
3Reliability
If deep trench isolation is implemented to separate polysilicon from substrate, then voltage balance is improved, but manufacturing complexity increases
Solution Approach 1:
The dielectric layer is segmented into multiple sub-layers with different materials and functions: a first dielectric sub-layer (500-700 Å) for primary charge isolation, and a second dielectric sub-layer (200-300 Å) for additional isolation and interface protection. This segmentation approach achieves superior voltage balance while maintaining manufacturability through standardized deposition processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dielectric layer effectively reduces deep trench inductive charge, improving wafer yield and preventing gate oxide damage, especially in trenches deeper than 2 micrometers, by maintaining a balanced voltage during processing.
Implementation Method 1
A dielectric layer is formed at the bottom of deep trenches to isolate polysilicon from the substrate silicon
Implementation Method 2
comprising multiple sub-layers of silicon oxide, with specific thickness ranges to prevent excessive heat dissipation
Data Source
AI summary
Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.