SOI Deep Trench Isolation Structure for Process Charging Damage
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Solution Overview
Problem
Deep trench semiconductor structures, particularly in silicon-on-insulator (SOI) transistors, are susceptible to process charging damage due to unbalanced voltage between the substrate and gate, leading to gate oxide damage, which existing technologies have not adequately addressed.
Innovation Solution
A dielectric layer is formed at the bottom of deep trenches to isolate polysilicon from the substrate silicon, comprising multiple sub-layers of silicon oxide, with specific thickness ranges to prevent excessive heat dissipation and reduce inductive charge, thereby maintaining a balanced voltage during processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep trenches are formed in SOI substrate, then bipolar device performance is improved, but process charging damage occurs due to unbalanced voltage between substrate and gate
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the polysilicon gate and the silicon substrate in deep trench regions. This dielectric layer acts as a mediator that prevents direct charge coupling, thereby eliminating the unbalanced voltage condition that causes process charging damage while allowing the deep trench bipolar device to maintain its performance benefits.
Solution Approach 2:
The dielectric layer is formed in advance during the fabrication process, before charging damage can occur during subsequent processing steps. This preliminary protective action prevents the harmful voltage imbalance from developing by blocking the charge transfer path between substrate and gate.
2Object-affected harmful factors
If dielectric layer thickness is increased to reduce inductive charge, then process charging damage is reduced, but heat dissipation capability deteriorates
Solution Approach 1:
The dielectric layer thickness is precisely controlled within a specific range (500-1000 Å) to optimize the balance between charge isolation and heat dissipation. This parameter optimization ensures that the dielectric layer is thick enough to reduce inductive charge effects but thin enough to maintain adequate thermal coupling between the polysilicon gate and silicon substrate.
Solution Approach 2:
The dielectric layer is selectively formed only in the deep trench regions where it is needed for charge isolation, while other regions maintain their original structure for optimal heat dissipation. This localized application allows different parts of the device to have different properties optimized for their specific functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dielectric layer effectively reduces deep trench inductive charge, improving wafer yield and preventing gate oxide damage, especially in trenches deeper than 2 micrometers, by maintaining a balanced voltage and enhancing heat dissipation.
Implementation Method 1
A dielectric layer is formed at the bottom of deep trenches to isolate polysilicon from the substrate silicon
Implementation Method 2
enhancing heat dissipation
Data Source
AI summary
Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.