SOI Contact and Isolation Trenches for High-Voltage ICs
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Solution Overview
Problem
High-voltage integrated circuits require specialized structures with thick device layers and effective isolation and contact trenches to withstand substantial voltages, which existing semiconductor-on-insulator (SOI) technologies do not adequately address.
Innovation Solution
The structure includes an isolation region in a first trench extending through the device layer to the buried oxide layer, a handle wafer contact in a second trench extending through both layers, and a doped region in the handle wafer, with an electrical insulator filling the trenches and a conductor formed in the contact trench, allowing for self-aligned and cost-effective formation of high-voltage device structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick device layer is used to provide sufficient volume for LDMOS drift region, then high-voltage circuit performance is improved, but standard well implants and isolation techniques become inadequate
Solution Approach 1:
The device layer is segmented into functional regions with different doping profiles. The drift region maintains thick undeoped or lightly-doped semiconductor material to withstand high voltages, while separate regions accommodate standard CMOS well implants. This segmentation allows simultaneous support for both high-voltage LDMOS devices and standard low-voltage CMOS circuits on the same thick device layer.
Solution Approach 2:
Different regions of the thick device layer are given different local properties: the drift region has high resistivity and appropriate thickness for voltage blocking, while other regions are doped to form source, drain, and well structures for standard CMOS devices. This local differentiation enables the thick device layer to serve multiple functional requirements simultaneously.
2Reliability
If isolation trenches are formed to electrically isolate devices, then device isolation is improved, but processing complexity increases
Solution Approach 1:
The isolation trench formation is merged with the contact trench formation process. Both types of trenches are etched simultaneously through the device layer using a single patterning and etching sequence, then filled with the same insulating material in one deposition step. This combining of processes reduces the overall processing complexity while achieving both isolation and contact functions.
Solution Approach 2:
The insulating material deposited in the trenches serves multiple functions simultaneously: it provides electrical isolation in the isolation trenches, forms the fill material for contact trenches after selective removal, and creates a planarized surface for subsequent processing. This multi-functionality reduces the number of separate process steps required.
3Reliability
If contact trenches extend through the buried oxide layer to the handle wafer, then contact resistance is reduced, but chip area increases
Solution Approach 1:
The contact trenches are formed to extend through the buried oxide layer to the handle wafer in advance, creating low-resistance contact paths before final device assembly. This preliminary action ensures that the handle wafer contacts are already in place to provide low resistance, eliminating the need for additional contact formation steps that would require extra space.
Solution Approach 2:
The contact trench structure is designed to nest efficiently within the chip layout. The trenches extend vertically through multiple layers (device layer, buried oxide, handle wafer) in a compact configuration, providing three-dimensional contact paths that minimize the horizontal footprint on the chip surface while achieving low resistance connections to the handle wafer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the fabrication of high-voltage integrated circuits with improved electrical isolation and reduced resistance, enhancing the performance and efficiency of high-voltage device structures while reducing chip area and processing costs.
Implementation Method 1
The first isolation region is comprised of an electrical insulator
Implementation Method 2
The handle wafer contact is comprised of an electrical conductor
Implementation Method 3
a doped region in the handle wafer
Data Source
AI summary
Structures that include contact trenches and isolation trenches, as well as methods for forming structures including contact trenches and isolation trenches. A contact trench is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate to a buried oxide layer of the SOI substrate. An isolation trench is formed that extends through the device layer to the buried oxide layer. An electrical insulator is deposited that fills the contact trench and the first isolation trench. The electrical insulator is removed from the contact trench. After the electrical insulator is removed from the contact trench, an electrical conductor is formed in the contact trench. The electrical contact may be coupled with a doped region in a handle wafer of the SOI substrate.