SOI VLSI Substrate Integration with High-Transparency Upper Layer
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Solution Overview
Problem
Advanced SOI VLSI technologies face challenges in integrating photonic devices due to the thin buried oxide layer, which leads to optical and RF signal losses, and struggle with accommodating high-performance passive devices within the limited chip space.
Innovation Solution
The integration of photonic and electronic devices is achieved by replacing the semiconductor substrate with a prefabricated upper layer of high transparency and resistivity, such as glass or quartz, which includes structures for photonic and electronic components, thereby minimizing optical and RF signal losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a thin buried oxide layer (150 nm) is used in SOI VLSI technology, then manufacturing cost is reduced and process compatibility is improved, but optical signal loss increases and RF signal loss increases
Solution Approach 1:
The patent divides the substrate into two separate layers: a thin buried oxide layer (150 nm) for manufacturing compatibility and a separate thick handle layer (greater than 200 nm) for optical confinement. This segmentation allows each layer to fulfill its specific function independently, resolving the contradiction between low manufacturing cost and low optical signal loss.
Solution Approach 2:
The patent adds a vertical dimension to the substrate structure by introducing a handle layer beneath the thin buried oxide layer. This dimensional expansion creates a multi-layer configuration where the thin oxide maintains process compatibility while the thick handle layer provides the necessary optical confinement, thereby reducing optical signal loss without increasing manufacturing complexity.
2Ease of manufacture
If a thin buried oxide layer (150 nm) is used in SOI VLSI technology, then manufacturing cost is reduced and process compatibility is improved, but RF signal loss increases
Solution Approach 1:
The patent segments the substrate into a thin buried oxide layer for manufacturing ease and a thick handle layer for RF signal confinement. This segmentation enables the thin oxide to maintain process compatibility while the thick handle layer provides the necessary electrical isolation and signal confinement to reduce RF signal loss.
3Device complexity
If chip space is limited in SOI VLSI structures, then manufacturing complexity is reduced, but accommodation of high-performance passive devices becomes difficult
Solution Approach 1:
The patent utilizes the vertical dimension by introducing a handle layer beneath the thin buried oxide layer. This vertical expansion provides additional space for passive devices without increasing the horizontal chip footprint, thereby accommodating high-performance passive devices while maintaining low manufacturing complexity.
Data Source
AI summary
According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.