SOI Voltage Generation Circuit Reducing Chip Area
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Solution Overview
Problem
Existing positive and negative voltage generation circuits in RF and microwave applications require a large chip area due to the need for multiple transistor switches and complex control signals, which increases static current and chip size, especially when generating voltages under DC bias conditions.
Innovation Solution
A positive/negative voltage generation circuit using only two MOS transistors and a single-phase clock signal, leveraging parasitic diodes and capacitors to generate voltages, reducing the complexity and chip area by simplifying the circuit structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If charge pump circuit with multiple transistor switches is used to generate positive and negative voltages, then voltage generation capability is improved, but chip area increases
Solution Approach 1:
The patent combines the positive voltage generation circuit and negative voltage generation circuit into a single integrated structure. The first charge pump circuit generates positive voltage while the second charge pump circuit generates negative voltage, and both circuits share common control logic and clock signals, merging multiple functions into one unified circuit block that reduces overall chip area.
Solution Approach 2:
The control circuit generates multiple control signals (first control signal, second control signal, third control signal, fourth control signal) from a single clock signal, making the control circuit universal for managing all four transistor switches. This multi-functional control approach eliminates the need for separate control circuits for each charge pump, reducing the total component count and chip area.
2Manufacturing precision
If multiple transistor switches are used to control charging and discharging, then voltage control precision is improved, but device complexity increases
Solution Approach 1:
The patent uses periodic clock signals to control the charging and discharging cycles of the capacitors. The first clock signal controls the first charge pump circuit to charge capacitor C1 to positive voltage, while the second clock signal controls the second charge pump circuit to charge capacitor C2 to negative voltage. This periodic control simplifies the timing management compared to complex multi-phase non-overlapping clocks, reducing device complexity while maintaining precise voltage control.
Solution Approach 2:
The circuit uses the inherent properties of the transistor switches and capacitors to automatically regulate voltage levels. The transistor switches M1-M4 and capacitors C1-C2 work together with the control signals to automatically charge and discharge, maintaining stable positive and negative voltage outputs without requiring additional voltage regulation circuits or complex control logic.
3Loss of energy
If large size transistor switches are used to reduce on-resistance, then energy loss is reduced, but chip area increases
Solution Approach 1:
The patent optimizes the transistor switch parameters by using standard-sized transistors with carefully selected width-to-length ratios (W/L) that balance on-resistance and area requirements. The control signal voltage levels are also optimized to ensure adequate drive strength without requiring oversized transistors. This parameter optimization allows smaller transistor switches to achieve acceptable on-resistance values, reducing chip area while maintaining low energy loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces chip area usage while maintaining voltage generation capabilities, protecting switch transistors and requiring less control complexity, resulting in a more efficient and compact circuit design.
Implementation Method 1
leveraging parasitic diodes and capacitors to generate voltages
Implementation Method 2
the size of the transistor switch that controls the charging and discharging of the capacitor must be large enough to reduce on-resistance
Data Source
AI summary
A silicon-on-insulator (SOI) based positive/negative voltage generation circuit includes: an inverter including an NMOS transistor and a PMOS transistor, a first transfer capacitor coupled to the PMOS transistor, a first output capacitor, a second transfer capacitor coupled to the NMOS transistor, a second output capacitor, a first diode disposed between the first transfer capacitor and the first output capacitor, a second diode disposed between the second transfer capacitor and the second output capacitor, one end of the first output capacitor is coupled to the ground, one end of the second output capacitor is coupled to the ground; wherein an output voltage of the inverter is controlled by a single-phase clock to flip periodically, charge the first transfer capacitor through a parasitic diode of the PMOS transistor, and charge the second transfer capacitor through a parasitic diode of the NMOS transistor.