SOI Wafer BESOI Process With BF2 Etch Stop and Low Defect Density
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Solution Overview
Problem
The semiconductor industry faces challenges in producing thin silicon-on-insulator (SOI) wafers due to high defect density in the BESOI process, which leads to low yield and poor electrical performance, and the layer transfer process requires specialized equipment not commonly available in semiconductor foundries.
Innovation Solution
A new process flow involving ion implantation of BF2+ species, followed by annealing, epitaxy, thermal oxidation, and wafer bonding, using a Si:B:F layer as a second etch stop and metal getter to suppress oxidation-induced stacking faults and facilitate standard equipment use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If BESOI process is used to manufacture SOI wafers, then thick SOI can be produced, but high defect density and low yield result
Solution Approach 1:
The patent applies preliminary action by performing ion implantation of BF2+ species and forming the Si:B:F etch stop layer before wafer bonding. This preliminary preparation of the device wafer with controlled dopant distribution enables subsequent selective removal of the p- epi layer and precise thickness control of the cap silicon layer, producing high-quality thin SOI wafers with low defect density while maintaining high yield
Solution Approach 2:
The patent changes physical and chemical parameters by using BF2+ ion implantation to simultaneously introduce boron and fluorine dopants at controlled concentrations and depth profiles. The boron concentration is optimized to provide etch stop functionality, while fluorine suppresses oxidation-induced stacking faults. Thermal processing parameters (annealing temperature, oxidation temperature) are precisely controlled to achieve desired dopant activation and layer structure without generating defects
2Manufacturing precision
If layer transfer process is used to make thin SOI wafers, then high quality SOI can be produced, but specialized equipment is required
Solution Approach 1:
The patent introduces an intermediary Si:B:F etch stop layer formed by ion implantation that mediates between the p+ starting substrate and the cap silicon layer. This intermediary layer enables selective removal of the p- epi layer through chemical etching, allowing precise control of cap silicon thickness without requiring specialized ion implantation or wafer bonding equipment. The process can be implemented using standard semiconductor manufacturing equipment
Solution Approach 2:
The patent replaces mechanical thinning processes with chemical etching based on dopant distribution. Instead of mechanically removing material to achieve desired thickness, the process uses selective chemical etching of the p- epi layer enabled by the Si:B:F etch stop layer, substituting mechanical systems with chemical processes that are more precise and equipment-accessible
3Productivity
If BESOI process is used, then manufacturing capability is achieved, but oxidation induced stacking faults occur
Solution Approach 1:
The patent converts the harmful effect of oxidation into a beneficial outcome by intentionally introducing fluorine dopants during BF2+ ion implantation. The fluorine suppresses oxidation-induced stacking faults during thermal oxidation processing, transforming what would be a defect-generating process into a controlled step that produces high-quality oxide layers. The boron dopant simultaneously provides etch stop functionality, converting multiple potential harms into benefits
4Length of moving object
If thin SOI wafers are manufactured using standard BESOI process, then production is possible, but defect density remains high
Solution Approach 1:
The patent applies local quality by creating non-uniform dopant distribution within the silicon layer through ion implantation. The Si:B:F etch stop layer has localized high concentrations of boron and fluorine at specific depths, providing etch stop functionality and oxidation suppression precisely where needed. The cap silicon layer thickness can be precisely controlled by adjusting implantation parameters, enabling thin SOI wafers with low defect density while maintaining manufacturing capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in SOI wafers with lower defect density, improved electrical performance, and the ability to manufacture thin SOI wafers using standard equipment, comparable in quality to those produced by the Smart-Cut process.
Implementation Method 1
ion implantation of BF2+ species into p- epi laying on p+ starting substrate
Implementation Method 2
anneal at 450-580 C after the implant step
Implementation Method 3
epitaxy of silicon layer at temperature below 800 C
Implementation Method 4
thermal oxidation at temperature below 800 C
Implementation Method 5
wafer bonding
Data Source
AI summary
A process for making silicon on insulator wafer by bond and etch back—BESOI. A boron etch stop is formed by BF2+ ion implantation followed by solid phase epitaxy—SPE. Fluorine getters metals for OISF immunity of the final wafer. SPE activates boron above solubility limit thus facilitates high etch selectivity. Future cap silicon film is epitaxially grown over the boron etch stop at temperature that limits boron diffusion and boron deactivation. High temperature hydrogen bake step in epitaxy is replaced with Siconi of similar low temperature process. Buried oxide is thermally grown from portion of cap silicon layer at temperature limiting Boron diffusion and deactivation. Thus, SOI wafer design is the same as in layer transfer process—bonding interface is at the bottom interface of BOX; properties of final SOI wafer are equal to SOI made by layer transfer process—including cap silicon layer thickness variation, and OISF defect count. Advantage over the layer transfer—this process does not require non-standard equipment. Standard processing tool set readily available at semiconductor foundries is sufficient to run this process. Foundries can use this process for in house SOI wafer manufacturing.