High Resistivity SOI Wafer Charge Trapping Layer

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Solution Overview

Problem

High resistivity semiconductor-on-insulator wafers for RF devices face issues with parasitic power losses and harmonic distortion due to charge inversion or accumulation layers at the buried oxide/handle interface, which existing methods fail to adequately address.

Innovation Solution

A multilayer structure is formed with a semiconductor nitride layer, such as aluminum nitride, on a high resistivity semiconductor handle substrate, bonded with a donor substrate, and a wide bandgap layer is introduced at the interface between the handle wafer and the buried oxide to enhance charge trapping efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a high resistivity semiconductor handle substrate is used for RF devices, then parasitic power losses are reduced, but charge inversion or accumulation layers form at the buried oxide/handle interface causing harmonic distortion

Engineering Contradiction:

Improveparasitic power lossesVSAvoidcharge inversion or accumulation layers

Core Design Contradiction:

Loss of energyVSObject-generated harmful factors

Solution Approach 1:

A charge trapping layer composed of nanocrystalline silicon is introduced as an intermediary between the high resistivity handle substrate and the buried oxide layer. This intermediate layer captures and holds charge carriers that would otherwise form inversion or accumulation layers at the interface, thereby preventing harmonic distortion while maintaining the low loss properties of the high resistivity substrate

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The charge trapping layer is formed as a composite structure with nanocrystalline silicon embedded in an amorphous silicon matrix. This composite material provides optimal charge trapping capability while maintaining compatibility with the surrounding silicon-based device structure, effectively addressing the interface charge problem

Inventive Principle:

Principle #40Composite materials

2Manufacturing precision

If wafer bonding is used to create silicon-on-insulator structures, then layer transfer is achieved, but substrate loss occurs and thickness uniformity is poor for layers thinner than a few microns

Engineering Contradiction:

Improvelayer transferVSAvoidsubstrate loss

Core Design Contradiction:

Manufacturing precisionVSLoss of substance

Solution Approach 1:

A charge trapping layer is formed on the handle substrate before bonding with the device layer. This preliminary action ensures that charge trapping capability is established in advance, preventing interface charge formation that would compromise device performance, while the bonding process itself enables substrate recycling

Inventive Principle:

Principle #10Preliminary action

3Manufacturing precision

If the front surface of the donor wafer is bonded to the handle wafer through hydrophilic bonding, then layer transfer is achieved, but the bond is relatively weak and requires strengthening

Engineering Contradiction:

Improvelayer transferVSAvoidbond strength

Core Design Contradiction:

Manufacturing precisionVSStrength

Solution Approach 1:

The bonding process utilizes controlled parameter changes including temperature variation and plasma treatment to strengthen the hydrophilic bond between donor and handle wafers. The charge trapping layer formation also involves parameter changes in material structure (crystalline to nanocrystalline) to achieve optimal charge trapping while maintaining bond integrity

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The wide bandgap layer effectively traps charges, maintaining high resistivity even in the near-surface region, reducing parasitic power losses and harmonic distortions in RF devices.

Implementation Method 1

the wide bandgap layer effectively traps charges, maintaining high resistivity even in the near-surface region

Methodology Applied

Scientific EffectCharge trapping:

Implementation Method 2

reducing parasitic power losses and harmonic distortions in RF devices

Methodology Applied

Scientific EffectParasitic power loss reduction:

Data Source

PatentUS10483379B2High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss

Publication Date: 2019.11.19 GLOBALWAFERS CO LTD

AI summary

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a semiconductor nitride layer in contact with the semiconductor handle substrate, the semiconductor nitride layer selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof; a dielectric layer in contact with the semiconductor nitride layer; and a semiconductor device layer in contact with the dielectric layer.