SOI Wafer Surface Preparation for Atomistic-CMOS Integration
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Solution Overview
Problem
Integrating atomistic electronics with existing CMOS electronics is challenging due to the damage caused by preparatory steps required for atomistic electronics, such as high temperatures and acidic treatments, which can damage metallic interconnects and deplete dopants in CMOS electronics.
Innovation Solution
A method involving a silicon on insulator wafer with selective removal of semiconductor layers to create inactive and active regions, forming conductors for electrical circuits, and using resistive heating to remove native oxide layers from the active regions, allowing for the integration of atomistic electronics without damaging CMOS components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high temperature treatment (e.g., 1100 degrees Celsius) is applied to prepare pristine silicon surface for atomistic electronics, then surface quality is improved, but CMOS electronics are damaged due to metal interconnect melting and dopant depletion
Solution Approach 1:
The wafer is divided into two distinct regions: an active region for atomistic electronics requiring high temperature treatment, and an inactive region containing CMOS electronics that must be protected. This spatial segmentation allows different thermal treatments to be applied to different regions, resolving the contradiction between surface quality improvement and CMOS protection.
Solution Approach 2:
The invention applies high temperature treatment locally only to the active region where atomistic electronics are to be formed, while the inactive region containing CMOS electronics remains at lower temperature. This local quality approach enables the pristine silicon surface to be achieved where needed without exposing the entire wafer to damaging temperatures.
2Manufacturing precision
If acidic treatment is applied to remove native oxide from silicon surface for atomistic electronics, then surface cleanliness is improved, but CMOS metallic interconnects are damaged
Solution Approach 1:
The wafer structure is segmented into active and inactive regions, allowing acidic treatment to be applied selectively to the active region only. The inactive region containing CMOS interconnects is excluded from the acidic environment, thus achieving surface cleanliness where needed while protecting sensitive metal interconnects.
Solution Approach 2:
Acidic treatment is applied with local quality control, affecting only the active region surface while leaving the inactive region untouched. This enables the silicon surface in the active region to be cleaned of native oxide and contaminants without exposing the CMOS metallic interconnects in the inactive region to corrosive acids.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the preparation of a pristine silicon surface suitable for atomistic electronics while preserving existing CMOS electronics, facilitating the integration of both technologies on a common silicon substrate without damaging metallic interconnects or depleting dopants.
Implementation Method 1
selectively treating the first active region of the wafer to remove a native oxide layer from the first portion of the semiconductor layer, wherein the treating comprises energizing the electrical circuit with an external power source to induce resistive heating of the first portion of the semiconductor layer
Data Source
AI summary
A method for treating a wafer is provided with a portion of a semiconductor layer is selectively removed from the wafer so as to create an inactive region of the wafer surrounding a first active region of the wafer. The inactive region of the wafer has an exposed portion of an insulator layer, but none of the semiconductor layer. The first active region of the wafer includes a first portion of the semiconductor layer and a first portion of the insulator layer. At least one conductor is formed in contact with the first portion of the semiconductor layer, such that the conductor and the first portion of the semiconductor layer form a portion of an electrical circuit. The first active region of the wafer is selectively treated to remove a native oxide layer from the first portion of the semiconductor layer. A resulting wafer is also disclosed.