SOI Wafer Manufacturing via Continuous Epitaxial Growth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high cost and complexity of manufacturing SOI substrates with high crystal quality and the challenge of integrating SOI and bulk type MISFETs on a single substrate due to difficulties in forming high-quality SOI structures using conventional ELO methods, which limits the production of low-power, high-speed semiconductor devices with high blocking voltage capabilities.
Innovation Solution
A method involving selective epitaxial growth and hydrogen annealing to form SOI structures on bulk substrates, where epitaxial growth is continued without temperature reduction, and hydrogen annealing is used to planarize the substrate, eliminating stacking faults and enabling the coexistence of SOI and bulk regions on a single substrate, thus reducing manufacturing costs and process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional epitaxial lateral overgrowth methods are used to manufacture SOI substrates, then SOI structures can be formed on bulk substrates, but the substrate surface becomes non-uniform with stacking faults and crystal defects
Solution Approach 1:
The invention changes the temperature parameter by performing etching and flattening processes without allowing the substrate temperature to decrease from the epitaxial growth temperature. This parameter change prevents stress-induced stacking faults while achieving surface planarization, thus resolving the contradiction between manufacturing ease and manufacturing precision
Solution Approach 2:
The invention maintains continuous heating during the etching and flattening processes, ensuring the substrate temperature never drops from the growth temperature. This continuous thermal action prevents crystal defects while achieving surface uniformity, resolving the contradiction between cost-effectiveness and quality
2Adaptability or versatility
If SOI and bulk type MISFETs are integrated on a single substrate, then device functionality is enhanced, but manufacturing complexity increases due to process incompatibility
Solution Approach 1:
The invention applies local quality by forming SOI structures only in specific regions where low-power and high-speed devices are needed, while leaving other regions as bulk substrate for high-blocking voltage devices. This localized approach allows integration of different device types on a single substrate without requiring complex differentiating processes
Solution Approach 2:
The invention makes the substrate multi-functional by enabling it to support both SOI and bulk type MISFETs through a unified manufacturing process. The etching and flattening method works for both device types, eliminating the need for separate processing lines and reducing overall manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the production of SOI substrates with high crystal quality and uniform film thickness at lower costs, enabling the integration of high-blocking voltage devices and low-power, high-speed SOI MISFETs on the same substrate, simplifying the manufacturing process and reducing substrate area requirements.
Implementation Method 1
hydrogen annealing to planarize the epitaxial growth surface
Implementation Method 2
selective epitaxial growth on a bulk substrate
Implementation Method 3
hydrogen annealing to planarize the epitaxial growth surface
Data Source
AI summary
It is an object of the present invention to provide a method of manufacturing an SOI wafer at low cost and with high yield. It is another object of the present invention to provide a semiconductor device including also bulk type MISFETs used as high voltage regions and a method of manufacturing the same without using complicated processes and increasing the size of a semiconductor chip.The method of manufacturing a semiconductor device comprises selectively epitaxially growing a single-crystal Si layer and continuously performing the epitaxial growth without bringing a substrate temperature increased during the growth to room temperature even once. An epitaxially grown surface is then etched and planarized. The substrate temperature is then cooled down to the room temperature.