SOI Wafer Fabrication Edge Roll Off Defect Reduction
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Solution Overview
Problem
Existing methods for fabricating silicon on insulator (SOI) wafers often result in defects, such as voids, near the outer periphery, which limits the utilization of semiconductor wafers in device fabrication, particularly for larger 300 mm and 450 mm wafers.
Innovation Solution
Determining the edge roll off (ERO) value using the second derivative of the wafer's height profile and selecting wafers with an ERO of more than approximately 50 nm, 100 nm, or 150 nm for bonding, which reduces peripheral defects by ensuring proper attachment and minimizing bonding-related defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wafer fabrication methods are used, then production efficiency is maintained, but voids and defects occur in the outer periphery of the wafer
Solution Approach 1:
The patent applies preliminary action by measuring and determining the Edge Roll Off (ERO) value of wafers before the bonding process. This pre-assessment allows selection of wafers with appropriate ERO characteristics (more than approximately 50 nm, 100 nm, or 150 nm) to prevent void formation during subsequent bonding, thereby eliminating defects before they occur rather than addressing them after bonding.
2Ease of manufacture
If wafer bonding is performed without ERO selection, then manufacturing process is simple, but defects are generated in the outer periphery
Solution Approach 1:
The patent replaces complex mechanical control of bonding parameters with a simpler measurement-based selection approach. Instead of controlling bonding pressure, temperature, and timing to achieve perfect bonding, the method substitutes this with measuring the ERO value and selecting wafers that meet predetermined thresholds, thereby achieving high bonding precision through a simpler measurement-based system.
3Reliability
If ERO selection criteria are applied, then defect reduction is achieved, but additional measurement and selection steps are required
Solution Approach 1:
The patent applies parameter changes by establishing specific ERO value thresholds (more than approximately 50 nm, 100 nm, or 150 nm) as selection criteria. This transforms the bonding process from one requiring complex real-time control to a simpler process where wafers are selected based on predetermined parameter ranges, reducing process complexity while maintaining high bonding reliability.
4Productivity
If wafers with small ERO values are used, then material utilization is high, but peripheral defects increase
Solution Approach 1:
The patent implements feedback by measuring the ERO value of each wafer and using this information to determine whether the wafer is suitable for bonding. This feedback loop ensures that only wafers meeting the predetermined ERO criteria are selected, preventing defective wafers from entering the bonding process and thereby maintaining both high utilization rates and high quality standards.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly reduces the number of voids and defects in compound-material wafers, especially in larger 300 mm wafers, improving the yield and quality of SOI wafers by ensuring accurate bonding and reducing defects in the transferred thin layers.
Implementation Method 1
attaching, in particular by bonding, the one wafer to the other
Data Source
AI summary
The present invention provides improved methods for fabricating compound-material wafers, in particular a silicon on insulator type wafer. The improved methods lead to reduced numbers of deflects arising on or near the periphery of the wafers. In a first method, wafers are selected in dependence on edge roll off values determined at about 0.5-2.5 mm away from the edge of the wafer, where edge roll off values are determined in dependence on the second derivative of the wafer height profiles. In a second method, wafers selected according to the first method are further processed by bonding, forming a splitting layer, and detaching the two wafers at the splitting layer.