SOI Wafer Etch Release via Buried Oxide Segmentation
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Solution Overview
Problem
Current MEMS device fabrication processes, such as deep reactive ion etching (DRIE), face challenges with wafer fragility, inefficient thermal conduction, and labor-intensive cleaning due to high aspect ratio etching and adhesive bonding, leading to suboptimal geometry and increased manufacturing costs.
Innovation Solution
A method using a silicon on insulator (SOI) wafer with a buried oxide layer, where the device layer is bonded to a handle layer, allowing for a dry etch process with hydrofluoric acid and nitrogen carrier gas to release devices efficiently, reducing stiction and thermal issues, and employing infrared metrology for etch process characterization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If deep reactive ion etching (DRIE) is performed on a silicon wafer to form high aspect ratio structures, then the desired device geometry is achieved, but the wafer becomes fragile and prone to damage when completely etched through
Solution Approach 1:
The wafer is segmented into three distinct layers: a handle layer providing mechanical strength, a buried oxide bonding layer for release, and a device layer for patterning. This segmentation allows the handle layer to maintain wafer strength while the device layer undergoes high aspect ratio etching without compromising overall structural integrity.
Solution Approach 2:
A buried oxide layer serves as an intermediary between the handle layer and device layer. This oxide layer acts as a sacrificial bonding interface that can be selectively removed to release devices while the handle layer continues to provide mechanical support to the structure during processing.
2Temperature
If coolant material is supplied to the back side of the wafer during DRIE to cool the wafer, then thermal control is improved, but once the wafer is perforated the coolant action becomes ineffective and pressure in the etch chamber increases
Solution Approach 1:
The wafer structure is segmented with a dedicated handle layer that remains intact during etching, providing a continuous cooling pathway for the coolant. This prevents chamber pressure buildup while maintaining effective thermal control throughout the high aspect ratio etching process.
3Strength
If a silicon wafer is bonded to a carrier using an adhesive bonding layer to prevent fragility during etching, then wafer strength is improved, but the adhesive is a poor thermal conductor causing wafer heating and the release process becomes labor-intensive
Solution Approach 1:
The bonding layer material is changed from organic adhesive to inorganic buried oxide, fundamentally altering thermal conductivity parameters. The oxide layer provides both mechanical bonding strength and superior thermal conduction, enabling efficient heat removal during etching while maintaining wafer integrity.
Solution Approach 2:
The buried oxide bonding layer provides self-release capability through selective chemical etching. The oxide layer can be removed by specific etchants to release devices without requiring manual intervention, making the process self-sufficient and eliminating labor-intensive cleaning steps.
4Strength
If adhesive bonding is used to attach the wafer to a carrier, then mechanical support is improved, but thermal conduction is inefficient leading to degraded etch quality and increased manufacturing cost
Solution Approach 1:
The bonding layer material is changed from organic adhesive to inorganic buried oxide, fundamentally altering thermal conductivity parameters. The oxide layer provides both mechanical bonding strength and superior thermal conduction, enabling efficient heat removal during etching while maintaining wafer integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control of high aspect ratio feature retention, reduces manufacturing time and costs, and improves the quality of etched structures by maintaining thermal control and avoiding labor-intensive cleaning, while enhancing the efficiency of the etch process and device handling.
Implementation Method 1
The dry etch process may comprise introducing an etchant comprising hydrofluoric acid into the etch chamber. The etchant may further comprise nitrogen carrier gas and anhydrous alcohol vapor.
Implementation Method 2
an infrared detection system positioned to detect infrared radiation from the wafer
Implementation Method 3
an infrared illuminator positioned to illuminate the wafer with infrared radiation
Data Source
AI summary
Systems and techniques for enhanced etch processes. For example, a substrate may be received in an etch chamber, where the substrate comprises a handle layer, a bonding layer in communication with the handle layer, and a device layer in communication with the bonding layer. The device layer may comprise a device layer patterned therein and having a bottom surface, where the bottom surface of the device is attached to the bonding layer. The bonding layer may comprise an oxide annealed at relatively low temperature. A dry etch process may be performed to release the bottom surface of the device from the bonding layer.