SOI Wafer Buried Insulator Thickness Design for Position Control
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Solution Overview
Problem
The variation in SOI layer thickness leads to inconsistent reflection rates when using reflected light for position control in device fabrication and inspection processes, making precise position control challenging and requiring separate mechanisms for SOI wafers compared to bulk silicon wafers.
Innovation Solution
Designing the thickness of the buried insulator layer in SOI wafers based on the wavelength of light used for position control, using the expression d=(1/2)×(λ/n)×A, where d is the thickness, n is the refractive index, and A is an arbitrary positive integer, to stabilize the reflection rate and match it with bulk silicon wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the SOI layer thickness varies in the plane of the SOI wafer, then the reflection rate of irradiation light varies widely, but this causes the position control of the SOI wafer to be inaccurate
Solution Approach 1:
The patent changes the physical parameter of the buried insulator layer thickness to a specific value (5-20 nm) that modifies the optical interference conditions. This parameter change causes the reflected light intensity to become insensitive to SOI layer thickness variations, thereby resolving the contradiction between manufacturing precision and measurement precision in position control
Solution Approach 2:
Instead of trying to control SOI layer thickness to achieve stable reflection, the patent inverts the approach by controlling the buried insulator layer thickness to achieve stable reflection. This inversion transfers the control parameter from the SOI layer to the buried insulator layer, solving the position control accuracy problem
2Measurement precision
If separate position control mechanisms are developed for SOI wafers, then position control accuracy can be improved, but device complexity and cost increase
Solution Approach 1:
The patent makes the buried insulator layer thickness serve multiple functions: it provides electrical insulation between the SOI layer and substrate, and simultaneously optimizes optical reflection characteristics for position control. This multi-functionality allows existing position control mechanisms to work effectively with SOI wafers without requiring separate specialized mechanisms, reducing device complexity and cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the reflection rate, enhancing the precision of position control and allowing the reuse of mechanisms from bulk silicon wafer processes, thereby reducing costs in device fabrication and inspection processes.
Implementation Method 1
Reflected light from the surface of the SOI wafer when the SOI wafer is irradiated with light is utilized for the position control
Data Source
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AI summary
The present invention is a method for manufacturing an SOI wafer that has an SOI layer formed on a buried insulator layer and that is to be used in a device fabrication process or an inspection process including a process of controlling a position of the SOI wafer on the basis of intensity of reflected light from the SOI wafer when the SOI wafer is irradiated with light having a wavelength λ. The method comprises the steps of: designing a thickness of the buried insulator layer of the SOI wafer on the basis of the wavelength λ of the light for use in the process of controlling the position that is to be implemented on the SOI wafer after manufacturing; and fabricating the SOI wafer having the SOI layer formed on the buried insulator layer having the designed thickness. As a result, there is provided a method for designing and manufacturing an SOI wafer that enables inhibition of variation in the reflection rate of light due to variation in the SOI layer thickness to improve precision of the position control of the SOI wafer and enables cost reduction by sharing position control mechanisms used in the device fabrication process or the inspection process using a bulk silicon wafer.