Bonded SOI Wafer Polishing Process Optimization

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Solution Overview

Problem

The manufacturing process for bonded SOI wafers requires excessive polishing steps to achieve a flat polycrystalline silicon surface, leading to reduced productivity and potential voids during bonding.

Innovation Solution

A method involving primary polishing of a chemically etched base wafer followed by deposition of a polycrystalline silicon layer, with subsequent secondary or finish polishing of the polycrystalline silicon layer surface, minimizes necessary polishing steps while ensuring a flat surface for bonding, using a base wafer with high resistivity and double-side primary polishing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple polishing stages (primary, secondary, finish polishing) are performed on the base wafer before depositing the polycrystalline silicon layer, then the surface flatness and roughness are improved, but the manufacturing complexity and time are increased

Engineering Contradiction:
Improvesurface flatnessVSAvoidpolishing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The base wafer surface is prepared in advance through chemical etching and single-stage primary polishing before depositing the polycrystalline silicon layer. This preliminary preparation ensures adequate surface flatness without requiring multiple sequential polishing stages, thereby reducing process complexity while maintaining manufacturing precision

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention changes the polishing parameters by performing only primary polishing with specific conditions (polishing stock removal of several μm) instead of the conventional multi-stage approach. This parameter modification achieves sufficient surface flatness for subsequent bonding without the need for secondary and finish polishing stages

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If multiple polishing stages are performed on the polycrystalline silicon layer after deposition, then the surface flatness is improved, but the productivity is reduced

Engineering Contradiction:
Improvesurface flatnessVSAvoidmanufacturing efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The base wafer is pre-prepared with adequate flatness through chemical etching and primary polishing before polycrystalline silicon deposition. This preliminary action ensures that the deposited layer inherits sufficient surface quality, eliminating the need for multiple subsequent polishing stages and thereby maintaining high productivity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention extracts and eliminates the secondary and finish polishing stages from the conventional multi-stage polishing process. By removing these redundant stages, the process time is reduced and productivity is improved while still achieving the required surface flatness for bonding

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If excessive polishing is performed to ensure a flat surface for bonding, then the bonding quality is improved, but voids may be generated and productivity is reduced

Engineering Contradiction:
Improvebonding qualityVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The base wafer surface is pre-treated with chemical etching and primary polishing to achieve adequate flatness before polycrystalline silicon deposition. This preliminary preparation ensures that the surface is sufficiently flat for high-quality bonding without requiring excessive subsequent polishing, thereby preventing void formation and maintaining productivity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention applies partial polishing action by performing only primary polishing with controlled stock removal instead of excessive multi-stage polishing. This partial action is sufficient to achieve the required surface flatness for bonding while avoiding the generation of voids and maintaining high manufacturing efficiency

Inventive Principle:
Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in a high-quality bonded SOI wafer with reduced voids and improved productivity by simplifying the polishing process while maintaining surface flatness, making it suitable for radio-frequency devices.

Implementation Method 1

primary polishing is performed with a polishing stock removal of about several μm to remove deformation to flatten the wafer surface

Methodology Applied
Scientific EffectAbrasion: Abrasion

Implementation Method 2

secondary polishing is performed with a polishing stock removal of about 1 μm to remove scratches formed at the primary polishing and to improve the surface roughness

Methodology Applied
Scientific EffectAbrasion: Abrasion

Implementation Method 3

depositing a polycrystalline silicon layer on the bonding surface side of the base wafer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 4

bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film

Methodology Applied
Scientific EffectDiffusion Welding: Diffusion Welding

Data Source

PatentUS10424484B2Method for manufacturing a bonded SOI wafer
Publication Date: 2019.09.24 SHIN ETSU HANDOTAI CO LTD
  • US10424484B2 patent drawing
  • US10424484B2 patent drawing

AI summary

Method for manufacturing a bonded SOI wafer by bonding a bond wafer and base wafer, each composed of a silicon single crystal, via an insulator film, including the steps: depositing a polycrystalline silicon layer on the base wafer bonding surface side, polishing the polycrystalline silicon layer surface, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the base wafer polycrystalline silicon layer and bond wafer via the insulator film; thinning the bonded bond wafer to form an SOI layer; wherein, in the step of depositing the polycrystalline silicon layer, a wafer having a chemically etched surface as base wafer; chemically etched surface is subjected to primary polishing followed by depositing the polycrystalline silicon layer on surface subjected to the primary polishing, and in the step polishing the polycrystalline silicon layer surface, which is subjected to secondary polishing or secondary and finish polishing.