SOI Wafer Top Silicon Thickness Layout for Mixed Device Types

The patent applies local quality by creating different top layer thicknesses in different regions of the same wafer. Specifically, first semiconductor devices have a first top layer thickness while second semiconductor devices have a second top layer thickness that is less than the first thickness. This allows each region to be optimized for its specific device type, enabling both fully depleted and partially depleted devices on the same wafer while maintaining manufacturing simplicity through a unified process approach.

The patent applies segmentation by dividing the wafer into different regions with different top layer thicknesses. The manufacturing process is segmented into stages: forming the top layer across the entire wafer, then selectively removing portions of the top layer in specific regions to create the thickness variation needed for different device types. This segmentation allows complex device characteristics to be achieved while maintaining a relatively straightforward manufacturing flow.