SOI Wafer Regions With Different Top Silicon Thicknesses

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Solution Overview

Problem

Existing semiconductor devices on a wafer often have the same top layer thickness, limiting their ability to have diverse characteristics and functionalities.

Innovation Solution

A method for fabricating semiconductor wafers with varying top layer thicknesses by etching and polishing silicon layers to form fully and partially depleted devices on a single substrate, utilizing a carrier wafer bonding process to create devices with different top silicon and BOX layer thicknesses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If all devices on a wafer are fabricated with the same top layer thickness, then manufacturing simplicity is maintained, but device diversity and functional versatility are limited

Engineering Contradiction:

Improvedevice diversityVSAvoidmanufacturing simplicity

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The wafer is divided into multiple regions with different top layer thicknesses. Some regions are fully etched through the top layer while other regions retain the full top layer thickness, allowing different device types to be fabricated in different regions of the same wafer

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the wafer are given different local properties by selectively etching the top layer in specific areas. This allows devices in etched regions to have different characteristics (e.g., fully depleted) compared to devices in non-etched regions (e.g., partially depleted)

Inventive Principle:

Principle #3Local quality

2Reliability

If the top layer is completely removed in certain regions, then fully depleted devices are achieved, but additional processing steps are required

Engineering Contradiction:

Improvedevice performanceVSAvoidprocessing steps

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The top layer is preliminarily etched in selected regions before final device fabrication. This preliminary etching creates the foundation for fully depleted devices while allowing the remaining top layer to protect and support partially depleted devices in other regions

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250248118A1Semiconductor wafer with devices having different top layer thicknesses

Publication Date: 2025.07.31 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A circuit includes a base silicon layer, a base oxide layer, a first top silicon layer, a second top silicon layer, a first semiconductor device, and a second semiconductor device. The base oxide layer is formed over the base silicon layer. The first top silicon layer is formed over a first region of the base oxide layer and has a first thickness. The second top silicon layer is formed over a second region of the base oxide layer and has a second thickness less than the first thickness. The first semiconductor device is formed over the first top silicon layer and the second semiconductor device is formed over the second top silicon layer. The ability to fabricate a top silicon layers with differing thicknesses can provide a single substrate having devices with different characteristics, such as having both fully depleted and partially depleted devices on a single substrate.