SOI Substrate Wafer Stack for Reducing Parasitic Surface Conduction
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Solution Overview
Problem
High-resistivity silicon-on-insulator (SOI) substrates used in radio-frequency applications suffer from parasitic surface conduction and harmonic distortions due to fixed positive electrical charges in the buried oxide layer, leading to substrate-related losses and crosstalk, which are not completely eliminated by existing trap-rich substrate structures.
Innovation Solution
A method for producing an SOI substrate with a high density of surface traps by forming a stack of polycrystalline silicon layers separated by distinct interface zones, where the last layer has a thickness less than 20% of the total stack, to increase grain boundary density and trap density at the substrate-BOX interface, thereby reducing parasitic capacitance and harmonic distortions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a high-resistivity substrate is used, then substrate-related losses are reduced, but parasitic surface conduction remains due to fixed positive charges in the BOX layer
Solution Approach 1:
A polysilicon layer is introduced as an intermediary between the monocrystalline substrate and the BOX layer. This intermediate layer contains grain boundaries that act as charge traps, capturing free carriers and preventing parasitic surface conduction while maintaining the low-loss properties of the high-resistivity substrate.
Solution Approach 2:
The electrical properties of the substrate structure are modified by changing the material composition and introducing a polysilicon layer with different electrical characteristics. This changes the charge distribution and trap density parameters to eliminate parasitic conduction paths.
2Object-affected harmful factors
If the polysilicon layer thickness is increased to improve trap density, then parasitic conduction is reduced, but the average grain width at the polysilicon-BOX interface increases, reducing trap effectiveness
Solution Approach 1:
The polysilicon layer is segmented into multiple thinner layers separated by interface zones with distinct structures. This segmentation maintains a high density of grain boundaries and charge traps at the polysilicon-BOX interface while preventing excessive grain growth that would occur in a single thick layer.
Solution Approach 2:
Instead of controlling grain size in a single thick layer, the solution transitions to a multi-layer structure where the vertical dimension is used to create multiple interfaces. This increases the total trap density by distributing traps across multiple interfaces rather than relying on a single interface with controlled grain size.
3Ease of manufacture
If a single thick polysilicon layer is used, then manufacturing is simpler, but grain boundaries are insufficient to provide adequate charge trapping
Solution Approach 1:
The single thick polysilicon layer is divided into multiple thinner layers. Each layer contributes to the overall charge trapping capability, and the cumulative effect of multiple interfaces provides superior trap density compared to a single layer, while remaining compatible with standard deposition processes.
Solution Approach 2:
Multiple polysilicon layers are nested between the substrate and the BOX layer, with each layer containing grain boundaries that act as charge traps. This nested structure maximizes the trap density within the available vertical space without requiring excessive thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic surface conduction and harmonic distortions, improving the resistivity and performance of RF components by increasing the density of grain boundaries and charge traps, ensuring consistent electrical parameters across transistors.
Implementation Method 1
The formation of the interface zone comprises exposing the upper face of the first layer to an oxidizing environment to oxidize said upper face
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
Method for production of a semiconductor wafer suitable for the manufacture of an SOI substrate, comprising the following steps: - production, on the upper face (2) of a semiconductor support (1), of a first layer (4) of polycrystalline semiconductor; then - formation of an interface area (12) on the upper face (7) of said first layer (4), the interface area (12) having a structure distinct from the crystalline structure of said first layer (4); then - production on said interface area (12) of a second layer (14) of polycrystalline semiconductor.