Thermally Stable Charge Trapping Layer for RF SOI Wafers
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Solution Overview
Problem
Conventional methods for creating charge trapping layers in semiconductor-on-insulator wafers, such as those used in RF devices, suffer from reduced effectiveness due to thermal processing, which anneals out defects and reduces charge trapping efficiency.
Innovation Solution
A method involving hydrogen ion implantation at multiple depths followed by a two-step thermal treatment to form a three-dimensional network of dislocations and cavities in the handle substrate, which acts as a thermally stable charge trapping layer, preserving its effectiveness even under high temperature annealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional thermal processing is used to manufacture semiconductor-on-insulator wafers, then manufacturing processes can be simplified, but charge trapping effectiveness is reduced due to annealing out of defects
Solution Approach 1:
The patent applies preliminary action by forming the charge trapping layer through hydrogen ion implantation and thermal processing before the final device fabrication steps. The charge trapping layer is created in advance during wafer preparation, allowing subsequent device manufacturing to proceed without additional complex processing while the pre-formed layer maintains its charge trapping effectiveness throughout device fabrication.
2Strength
If high temperature annealing is applied to strengthen wafer bonding, then bond strength is improved, but charge trapping layer effectiveness is reduced due to defect annealing
Solution Approach 1:
The patent applies parameter changes by carefully controlling the thermal processing parameters - specifically using annealing temperatures and durations that are sufficient to strengthen the wafer bond through siloxane bond formation, while remaining below the threshold that would anneal out the hydrogen-induced defects in the charge trapping layer. This optimized thermal parameter regime allows simultaneous achievement of strong bonding and preserved charge trapping effectiveness.
3Reliability
If defects are introduced to create charge trapping layers, then charge trapping capability is enhanced, but thermal stability is reduced due to defect annealing
Solution Approach 1:
The patent applies parameter changes by precisely controlling the thermal processing parameters to create a stable defect structure. The hydrogen ion implantation followed by controlled annealing creates a specific defect configuration that is thermally stable at the annealing temperatures used for wafer bonding. The parameters are optimized so that the defects survive the thermal processing required for device fabrication while still providing effective charge trapping.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The resulting thermally stable charge trapping layer enhances the performance of RF devices by maintaining resistivity and reducing parasitic effects, allowing for the fabrication of high-quality radiofrequency chips.
Implementation Method 1
implanting hydrogen ions to a first implant depth, IMD1, corresponding to a plane of a first peak hydrogen ion concentration in the front surface region of the single crystal semiconductor handle substrate
Implementation Method 2
annealing the hydrogen ion implanted single crystal semiconductor handle substrate at a temperature and a duration sufficient to form a three-dimensional network of dislocations and cavities
Data Source
AI summary
A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (BOX) of the final semiconductor-on-insulator structure. The handle substrate comprising the stable carrier traps is manufactured by hydrogen ions implantation occurring using at least two different energies, followed by a 2-step thermal treatment. The thermally stable defect structures prepared thereby is stable to anneal at temperatures of at least 1180° C. The defect structure comprises 3-dimensional network of nano-cavities interconnected by dislocations. This wafer can be used as a handle wafer for fabricating silicon-on-insulator (SOI) wafers and further fabricating radio frequency (RF) semiconductor devices.