SOI Wafer Vertical Integration for Compact ICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing vertical integration techniques for integrated circuits (ICs) face limitations in reducing die area and increasing component density without increasing die volume and weight, which is crucial for compact and lightweight electronic devices like smartphones and tablets.
Innovation Solution
The method involves forming multiple active layers on a semiconductor-on-insulator (SOI) wafer by inverting the SOI wafer and bonding it with a handle wafer, allowing for monolithic integration of CMOS devices and MEMS devices with reduced die area and increased component density, using a monolithic fabrication process that eliminates the need for multiple substrates and complex bonding steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple active layers are formed on an SOI wafer using conventional vertical integration techniques, then component density increases, but die area and weight increase
Solution Approach 1:
The patent inverts the conventional approach by forming the first active layer on the backside of the SOI wafer rather than on the frontside. This inversion allows the first active layer to be positioned below the buried oxide layer, enabling vertical stacking of multiple active layers without increasing the die footprint, thus resolving the contradiction between increasing component density and maintaining reduced die area
Solution Approach 2:
The patent transitions from planar integration to three-dimensional vertical integration by stacking multiple active layers at different depths (frontside and backside of the SOI wafer, above and below the buried oxide). This dimensional change allows significant increase in component density while maintaining the same die area footprint
2Quantity of substance
If multiple active layers are formed on an SOI wafer using conventional vertical integration techniques, then component density increases, but die volume and weight increase
Solution Approach 1:
By inverting the formation sequence and positioning the first active layer on the backside below the buried oxide, the patent achieves vertical stacking that increases component density without requiring additional die volume or weight, as all components are integrated within the existing SOI wafer structure
Solution Approach 2:
The patent nests multiple active layers within the thickness of the SOI wafer structure, with the first active layer embedded below the buried oxide and the second active layer formed on the frontside. This nesting approach increases component density while containing all components within the original die volume, preventing weight increase
3Quantity of substance
If multiple substrates are used for forming active layers, then component density increases, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of multiple active layers into a single integrated process on one SOI wafer substrate. By forming the first active layer on the backside and the second active layer on the frontside of the same wafer, the patent eliminates the need for multiple separate substrates and complex inter-substrate bonding, thus reducing manufacturing complexity while achieving high component density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a significant reduction in die area and an increase in component density, facilitating the integration of various devices like CMOS, MEMS, and acoustic resonators, while providing structural stability and simplifying the manufacturing process, thus addressing the need for compact and lightweight ICs.
Implementation Method 1
bonding the first active layer to a handle wafer, wherein the handle wafer provides structural support
Data Source
Figure 1~3
Figure 4~5
Figure 6
AI summary
An semiconductor on insulator wafer has an insulator layer between a substrate layer and a semiconductor layer. A first active layer is formed in and on the semiconductor layer. A second active layer is formed in and on the substrate layer. In some embodiments, a handle wafer is bonded to the semiconductor on insulator wafer, and the substrate layer is thinned before forming the second active layer. In some embodiments, a third active layer may be formed in the substrate of the handle wafer. In some embodiments, the first and second active layers include a MEMS device in one of these layers and a CMOS device in the other.