SOI Well Bias Circuit for NMOS/PMOS Leakage and Threshold Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices with silicon on insulator (SOI) technology face limitations in achieving both forward and reverse back biases without exceeding the threshold voltage of the PN junction, which restricts the co-integration of NMOS and PMOS transistors in the same well and increases manufacturing complexity.
Innovation Solution
A semiconductor device configuration that includes NMOS and PMOS transistors separated by a buried dielectric layer in the carrier substrate, with a power supply circuit generating voltages to provide neutral, forward, and reverse back bias conditions, allowing transistors to operate within nominal threshold voltages without exceeding the PN junction threshold, using tensile strained channels, silicon-germanium alloy channels, nitrogen-doped gate dielectric layers, and titanium nitride gates to modulate work functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If forward back bias is applied to lower threshold voltage and improve transistor performance, then transistor performance is improved, but current leakage increases
Solution Approach 1:
The patent implements dynamic back-bias control by applying different voltages to P-type and N-type wells through separate power supply circuits. The bias voltages can be dynamically adjusted between forward back-bias (improving performance) and reverse back-bias (reducing leakage) modes, allowing the system to optimize transistor characteristics in real-time based on operational requirements.
2Object-generated harmful factors
If reverse back bias is applied to reduce current leakage, then current leakage is reduced, but transistor performance deteriorates
Solution Approach 1:
The system enables dynamic switching between reverse back-bias mode (for leakage reduction) and forward back-bias mode (for performance optimization). The separate control circuits for P-type and N-type wells allow independent voltage adjustment, facilitating flexible transition between operational modes to balance leakage and performance requirements.
3Reliability
If normal wells configuration is used with forward back bias, then transistor performance is improved, but the potential difference is limited by the PN junction threshold voltage
Solution Approach 1:
The patent segments the well structure into separately controllable P-type and N-type wells, each with its own power supply circuit. This segmentation allows independent voltage control of each well type, enabling the application of higher back-bias voltages that exceed the traditional PN junction threshold limitations while maintaining proper transistor operation.
4Object-generated harmful factors
If flip wells configuration is used with reverse back bias, then current leakage is reduced, but the potential difference is limited by the PN junction threshold voltage
Solution Approach 1:
By segmenting the well control into independent P-type and N-type well power supplies, the system can apply reverse back-bias voltages with greater magnitude than traditional configurations. The separate control enables the potential difference between wells to exceed PN junction threshold limitations while maintaining leakage reduction benefits.
5Adaptability or versatility
If co-integration of normal wells with flip wells is attempted, then both forward and reverse back biases can be achieved, but surface occupation increases and transistors must be electrically isolated
Solution Approach 1:
The patent implements a universal well structure where both P-type and N-type wells can serve multiple functions: supporting both normal and flipped transistor configurations, enabling both forward and reverse back-bias modes, and providing electrical isolation when needed. This multi-functional design eliminates the need for separate well regions, reducing surface occupation while maintaining configuration versatility.
6Adaptability or versatility
If additional lateral isolation trenches are used to electrically isolate wells, then forward and reverse back biases can be achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The universal well structure with separate power supply circuits provides electrical isolation and supports multiple back-bias configurations without requiring additional lateral isolation trenches. The inherent structure of the separately controlled P-type and N-type wells naturally provides the necessary isolation, simplifying the manufacturing process while maintaining configuration flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the co-integration of NMOS and PMOS transistors in the same well with improved performance by adjusting threshold voltages, reducing current leakage, and enhancing carrier mobility without increasing manufacturing complexity.
Implementation Method 1
a power supply circuit configured to generate voltages in the P-type and N-type wells, so as to selectively provide neutral, forward and reverse back bias conditions to the NMOS transistor and to the PMOS transistor
Implementation Method 2
the at least one NMOS transistor includes a tensile strained channel region, in the respective semiconductor film
Implementation Method 3
the at least one PMOS transistor includes a compressively strained channel region, in the respective semiconductor film
Implementation Method 4
nitrogen-doped gate dielectric layers
Data Source
AI summary
The semiconductor device of a silicon on insulator type includes a NMOS transistor in a P-type well of the carrier substrate, a PMOS transistor in an N-type well of the carrier substrate, and a power supply circuit configured to generate voltages in the P-type and N-type wells, so as to selectively provide neutral, forward and reverse back bias conditions to the NMOS transistor and the PMOS transistor. The neutral back bias condition is achieved when a first non-zero negative voltage is applied to the P-type well and a first non-zero positive voltage is applied to the N-type well. The NMOS and PMOS transistors are configured to have nominal threshold voltages in the neutral back bias condition.