SOI Well Structure With Dual Buried Insulators for Low-Voltage Speed
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Solution Overview
Problem
Current semiconductor devices face challenges in scaling and voltage management due to the limitations of single buried insulation layers, which affect parasitic capacitance and leakage current during high-speed operation at low voltage.
Innovation Solution
A semiconductor device design incorporating two buried insulation layers with separate well structures and element separation films allows for independent body bias voltage application to transistors, enabling improved scaling and reduced parasitic capacitance and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single buried insulation layer is used, then the device structure is simple, but parasitic capacitance and leakage current increase during high-speed operation at low voltage
Solution Approach 1:
The single buried insulation layer is segmented into two separate buried insulation layers (first and second buried insulation layers) positioned at different depths. This segmentation allows independent electrical isolation of different transistor regions, reducing parasitic capacitance between adjacent transistors and enabling separate body bias voltage application to minimize leakage current in each region.
2Productivity
If the degree of integration is improved with fine pitch patterns, then more transistors can be packed, but scaling becomes more difficult due to increased interference and harder fabrication
Solution Approach 1:
The solution moves from a single-plane insulation approach to a multi-layer three-dimensional structure. By stacking buried insulation layers at different depths and using selective element separation films, the design achieves higher integration density vertically while maintaining manufacturability through standardized multi-layer fabrication processes.
3Device complexity
If body bias voltage cannot be applied independently to different regions, then the structure is simpler, but high-speed operation at low voltage is compromised
Solution Approach 1:
The body bias voltage application is segmented into independent control regions. The first and second buried insulation layers create electrically isolated zones that allow different body bias voltages to be applied to different transistor regions, enabling optimization of high-speed operation at low voltage for each region independently.
Data Source
AI summary
A semiconductor device includes: a substrate; a first buried insulation layer disposed on the substrate; a first well which is disposed on the first buried insulation layer in a first region defined by a first element separation film, and includes a first portion extending along an upper surface of the first buried insulation layer, and a second portion extending from the first portion in a direction from the substrate toward the first buried insulation layer; a second buried insulation layer disposed on the first portion of the first well; a first semiconductor film disposed on the second buried insulation layer; a first transistor on the first semiconductor film; and a second element separation film which separates the second buried insulation layer and the first semiconductor film from the second portion of the first well, on the first portion of the first well, wherein an upper surface of the second portion of the first well is placed on the same plane as an upper surface of the first element separation film.