SOI Well Tap With Asymmetric Sidewall Spacers

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Solution Overview

Problem

The formation of conductive contacts, such as well taps, in integrated circuits is challenging due to variations in topology and space constraints, particularly when formed on semiconductor-on-insulator substrates, which can lead to processing difficulties and occupation of valuable space.

Innovation Solution

A well tap structure is developed with first and second opposing sidewall surfaces, featuring a first sidewall spacer with a specific vertical height and a second sidewall spacer with a lesser height, positioned around the well tap, which extends through the buried insulation layer of an SOI substrate to contact a doped well region, allowing for precise formation and reduced spatial occupancy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a well tap is formed to contact the doped well region, then electrical connection is achieved, but the topology variation and processing complexity increase

Engineering Contradiction:
Improveelectrical connectionVSAvoidtopology variation
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The well tap contact structure is segmented into multiple components: a contact opening through the buried insulation layer, a conductive material filling the opening, and sidewall spacers positioned on opposing sides. This segmentation allows each component to be optimized independently while achieving reliable electrical connection without excessive topology variation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The sidewall spacers are positioned locally at specific locations adjacent to the well tap contact structure, providing localized control over the contact geometry and electrical connection properties without affecting the entire device topology

Inventive Principle:
Principle #3Local quality

2Reliability

If a well tap is formed to contact the doped well region, then electrical connection is achieved, but the occupied plot space increases

Engineering Contradiction:
Improveelectrical connectionVSAvoidplot space
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The well tap contact structure utilizes the vertical dimension by extending through the buried insulation layer, allowing electrical connection to be achieved in the depth direction rather than requiring additional lateral space. This dimensional transition reduces the horizontal plot space occupation while maintaining reliable electrical connection

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If the well tap structure is simplified, then manufacturing is easier, but processing precision and topology control deteriorate

Engineering Contradiction:
Improveformation processVSAvoidtopology control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The sidewall spacers are formed through self-aligned processes where the spacers automatically position themselves relative to the well tap contact structure. This self-service approach simplifies the manufacturing process by eliminating complex alignment steps while simultaneously achieving precise topology control through the inherent geometric relationships of the self-aligned structure

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11610843B2Well tap for an integrated circuit product and methods of forming such a well tap
Publication Date: 2023.03.21 GLOBALFOUNDRIES US INC
  • US11610843B2 patent drawing
  • US11610843B2 patent drawing
  • US11610843B2 patent drawing

AI summary

An illustrative device disclosed herein includes a doped well region and a conductive well tap conductively coupled to the doped well region, the conductive well tap including first and second opposing sidewall surfaces. In this example the device also includes a first sidewall spacer that has a first vertical height positioned around the conductive well tap and a second sidewall spacer positioned adjacent the first sidewall spacer along the first and second opposing sidewall surfaces of the conductive well tap, wherein the second sidewall spacer has a second vertical height that is less than the first vertical height.