3D SoIC Backside Bridge Interconnects for Low-Latency Chiplets
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Solution Overview
Problem
Conventional through-silicon via connections in integrated circuit packaging are inefficient in meeting high power-efficiency and low latency requirements due to long wiring paths.
Innovation Solution
The formation of backside bridge structures on a first-tier chip allows for face-to-back bonding of second-tier chips, utilizing damascene structures to create short electrical paths that bypass the need for through-silicon vias, enabling efficient power and signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon via connections are used for chiplet communication, then electrical connectivity between chips is achieved, but wiring paths become long resulting in high latency and low power efficiency
Solution Approach 1:
The patent transitions from conventional planar wiring to three-dimensional vertical interconnects by stacking chiplets. The through-silicon vias provide direct vertical electrical pathways through the substrate, enabling signals to travel in the third dimension (depth) rather than along lengthy surface routes, thereby reducing latency while maintaining connectivity.
Solution Approach 2:
The patent introduces an interposer substrate as an intermediary component between chiplets. This interposer contains through-silicon vias that act as mediators, providing direct vertical conduction paths that bypass the need for long lateral wiring through the main substrate, thus reducing signal transmission time while ensuring reliable electrical connection.
2Reliability
If through-silicon via connections are used for chiplet communication, then electrical connectivity between chips is achieved, but power efficiency deteriorates due to long wiring paths
Solution Approach 1:
The patent utilizes vertical stacking with through-silicon vias to create direct three-dimensional electrical pathways. This dimensional change allows power and signal transmission to occur vertically through the substrate rather than along extended lateral paths, significantly reducing the length of conductors and thereby minimizing resistive power losses.
Solution Approach 2:
The interposer substrate serves as a mediator with integrated through-silicon vias that provide efficient vertical conduction pathways. This intermediary structure optimizes power delivery by creating direct vertical routes that minimize current path length and resistance, improving overall power efficiency while maintaining reliable electrical connectivity.
3Ease of manufacture
If conventional packaging schemes are used, then manufacturing simplicity is maintained, but the system cannot meet high performance requirements for power efficiency and latency
Solution Approach 1:
The patent divides the integrated circuit system into separate chiplet modules that can be independently manufactured and then stacked. This segmentation allows each chiplet to be optimized separately while the modular stacking approach with standardized interposers maintains manufacturing simplicity, avoiding the need to redesign entire substrate routing while achieving low-latency vertical interconnects.
Solution Approach 2:
The interposer substrate acts as a mediator that standardizes the interface between chiplets. This intermediary component provides a uniform platform with pre-fabricated through-silicon vias, simplifying the packaging process by decoupling chiplet design from substrate routing complexity while enabling high-performance vertical connections that reduce latency.
Data Source
AI summary
A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.