3D SoIC Backside Bridge Structures for Chiplet Interconnects

Solution Overview

Problem

Conventional through-silicon via connections in integrated circuit packaging are inefficient in meeting high power-efficiency and low latency requirements due to long wiring paths.

Innovation Solution

The formation of backside bridge structures on a first-tier chip allows for face-to-back bonding of second-tier chips, utilizing pre-formed bridge structures to create short electrical paths, thereby improving power efficiency and reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through-silicon via connections are used for chiplet communication, then electrical connectivity between chiplets is achieved, but the wiring paths become long resulting in high latency and poor power efficiency

Engineering Contradiction:

Improveelectrical connectivityVSAvoidlatency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent transitions from conventional planar wiring to three-dimensional vertical interconnects by stacking chiplets and using through-silicon vias to create direct vertical electrical pathways. This dimensional change dramatically shortens the signal path length compared to lateral routing through the substrate, thereby reducing latency while maintaining reliable connectivity between chiplets.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces an interposer substrate as an intermediary component that facilitates direct vertical connections between chiplets. The interposer contains through-silicon vias that act as mediators, providing short electrical pathways that bypass the need for long lateral routing through the package substrate, thus reducing latency while ensuring reliable electrical connectivity.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If through-silicon via connections are used for chiplet communication, then electrical connectivity between chiplets is achieved, but the long wiring paths result in high energy consumption

Engineering Contradiction:

Improveelectrical connectivityVSAvoidpower efficiency

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent transitions from conventional planar wiring to three-dimensional vertical interconnects by stacking chiplets and using through-silicon vias to create direct vertical electrical pathways. This dimensional change dramatically shortens the signal path length compared to lateral routing through the substrate, thereby reducing latency while maintaining reliable connectivity between chiplets.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces an interposer substrate as an intermediary component that facilitates direct vertical connections between chiplets. The interposer contains through-silicon vias that act as mediators, providing short electrical pathways that bypass the need for long lateral routing through the package substrate, thus reducing latency while ensuring reliable electrical connectivity.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Ease of manufacture

If conventional through-silicon via connections are used, then chiplet bonding is achieved, but the wiring paths are long and cannot meet high power-efficiency and low latency requirements

Engineering Contradiction:

Improvechiplet bondingVSAvoidsignal transmission time

Core Design Contradiction:

Ease of manufactureVSLoss of time

Solution Approach 1:

The patent transitions from conventional planar wiring to three-dimensional vertical interconnects by stacking chiplets and using through-silicon vias to create direct vertical electrical pathways. This dimensional change dramatically shortens the signal path length compared to lateral routing through the substrate, thereby reducing latency while maintaining reliable connectivity between chiplets.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces an interposer substrate as an intermediary component that facilitates direct vertical connections between chiplets. The interposer contains through-silicon vias that act as mediators, providing short electrical pathways that bypass the need for long lateral routing through the package substrate, thus reducing latency while ensuring reliable electrical connectivity.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11462495B2Chiplets 3D SoIC system integration and fabrication methods

Publication Date: 2022.10.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.