SoIC Die Stacking Layout to Minimize Warpage and Delamination
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and reliability of electronic components while minimizing feature size, which requires efficient packaging solutions that reduce area usage and minimize warpage.
Innovation Solution
The implementation of System on Integrated Circuit (SoIC) structures, which involve stacking second semiconductor dies over a first semiconductor die, using dummy dies to laterally surround the second semiconductor dies, and a gap filling layer to encapsulate both, along with a chip-to-wafer bonding process and a hybrid bonding process that includes dielectric-to-dielectric and metal-to-metal bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor dies are stacked to increase integration density, then the number of components per area increases, but warpage and delamination issues worsen
Solution Approach 1:
The patent applies preliminary action by forming dummy dies before the final stacking process. These dummy dies are created on the first substrate to occupy spaces between active dies, providing structural support and stress distribution in advance. This pre-positioning of dummy structures prevents warpage and delamination during subsequent die stacking and bonding operations, resolving the reliability issue while maintaining high integration density.
Solution Approach 2:
The patent implements local quality by creating different types of dies (active semiconductor dies and dummy dies) in specific locations on the substrate. The dummy dies are strategically placed in interstitial spaces between active dies, providing localized structural reinforcement where needed. This spatial differentiation allows the structure to maintain uniform stress distribution and prevent warpage in critical areas while preserving the functionality of active components.
2Quantity of substance
If feature size is reduced to increase integration density, then more components fit in a given area, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies segmentation by dividing the substrate into multiple functional regions containing different types of dies (active semiconductor dies and dummy dies). This segmentation allows independent optimization of each region - active dies can be minimized in size for high density while dummy dies provide larger structural elements for stress management. The segmented approach enables precise control of feature sizes without compromising overall manufacturing precision.
3Stability of the object's composition
If gap filling material is used to encapsulate dummy dies, then structural support is improved, but the amount of material and area used increases
Solution Approach 1:
The patent extracts the structural support function from the gap filling material by implementing dummy dies that inherently provide mechanical support and stress distribution. The dummy dies are formed as solid structures that occupy the interstitial spaces, eliminating the need for extensive gap filling material. This extraction of the support function to a dedicated structural element (dummy die) reduces material consumption while maintaining or improving structural stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances integration density, improves reliability by minimizing warpage and delamination issues, and increases fabrication yields by reducing the amount of gap filling material needed.
Implementation Method 1
a chip-to-wafer bonding process and a hybrid bonding process that includes dielectric-to-dielectric and metal-to-metal bonding
Data Source
AI summary
An SoIC structure including a first semiconductor die, second semiconductor dies, dummy dies, and a gap filling layer is provided. The second semiconductor dies are disposed over and electrically connected to the first semiconductor die. The dummy dies are disposed over the first semiconductor die to laterally surround the second semiconductor dies. The gap filling layer is disposed on the first semiconductor die to laterally encapsulate the dummy dies and the second semiconductor dies.