SoIC Die Stacking with Fusion Bonding for Fine-Pitch Integration
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high integration density and efficient heat dissipation while maintaining a small footprint, particularly in forming stacking semiconductor structures with fine pitch and high performance applications.
Innovation Solution
The method involves bonding the backside of a top die to the front side of a bottom die through a fusion bonding process, forming conductive pillars on bonding pads, and creating a dielectric material around them, followed by a redistribution structure, enabling the integration of System on Integrated Chips (SoIC) for various semiconductor packages like Chip-On-Wafer-On-Substrate (CoWoS) and Integrated Fan-Out (InFO) packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Package-on-Package (PoP) technology is used to stack semiconductor packages, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor structure into multiple discrete layers including substrate, interposer, and multiple dies that can be independently fabricated and tested before final assembly. This segmentation allows each layer to be optimized separately, reducing overall manufacturing complexity while maintaining high integration density through precise stacking of these standardized segments.
Solution Approach 2:
The patent implements preliminary testing and characterization of individual dies and interposers before final assembly. Dies are tested on-wafer before singulation, and interposers are prepared with pre-formed TSVs and bonding pads. This preliminary action ensures quality control is established early, reducing rework and complexity in later assembly stages while enabling high integration density through pre-validated components.
2Quantity of substance
If Chip-On-Wafer-On-Substrate (CoWoS) structure is implemented, then functional density is improved, but process complexity increases
Solution Approach 1:
The patent designs the interposer as a universal platform that can accommodate multiple die types and configurations. The interposer provides standardized bonding pads, TSV structures, and electrical interconnection patterns that work across different die formulations (logic, memory, I/O). This multi-functionality enables high functional density through flexible mixing of die types while reducing process complexity by using a single standardized interposer platform for all connections.
Solution Approach 2:
The patent uses the interposer as an intermediary component that mediates between the substrate and multiple dies. The interposer contains TSVs and redistribution layers that automatically route signals between different die types without requiring complex direct bonding arrangements. This intermediary structure simplifies the overall process by providing a standardized mediation layer that handles the complexity of multi-die interconnections.
3Quantity of substance
If minimum feature size is repeatedly reduced to increase integration density, then component quantity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking. Instead of continuously reducing minimum feature size in the planar direction, the design stacks multiple dies and interposers in the vertical dimension. This dimensionality change allows integration density to increase through vertical stacking height rather than horizontal feature shrinkage, thereby reducing the stringency of minimum feature size precision requirements while maintaining high component quantity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high integration density and effective heat dissipation, simplifying fabrication, reducing production costs, and enabling flexible integration of different die types within SoICs, which can be integrated into various package types, including CoWoS and InFO packages, with fine pitch capabilities.
Implementation Method 1
bonding the backside of a top die to the front side of a bottom die through a fusion bonding process
Data Source
AI summary
A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.